mirror of https://github.com/VLSIDA/OpenRAM.git
69 lines
2.3 KiB
Python
69 lines
2.3 KiB
Python
from tech import drc
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import debug
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import design
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from vector import vector
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from hierarchical_predecode import hierarchical_predecode
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from globals import OPTS
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class hierarchical_predecode2x4(hierarchical_predecode):
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"""
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Pre 2x4 decoder used in hierarchical_decoder.
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"""
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def __init__(self, height=None):
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hierarchical_predecode.__init__(self, 2, height)
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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self.add_pins()
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self.add_modules()
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self.create_input_inverters()
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self.create_output_inverters()
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connections =[["inbar_0", "inbar_1", "Z_0", "vdd", "gnd"],
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["in_0", "inbar_1", "Z_1", "vdd", "gnd"],
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["inbar_0", "in_1", "Z_2", "vdd", "gnd"],
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["in_0", "in_1", "Z_3", "vdd", "gnd"]]
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self.create_nand_array(connections)
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def create_layout(self):
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""" The general organization is from left to right:
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1) a set of M2 rails for input signals
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2) a set of inverters to invert input signals
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3) a set of M2 rails for the vdd, gnd, inverted inputs, inputs
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4) a set of NAND gates for inversion
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"""
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self.setup_layout_constraints()
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self.route_rails()
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self.place_input_inverters()
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self.place_output_inverters()
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self.place_nand_array()
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self.route()
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self.DRC_LVS()
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def get_nand_input_line_combination(self):
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""" These are the decoder connections of the NAND gates to the A,B pins """
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combination = [["Abar_0", "Abar_1"],
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["A_0", "Abar_1"],
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["Abar_0", "A_1"],
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["A_0", "A_1"]]
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return combination
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def analytical_delay(self, slew, load = 0.0 ):
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# in -> inbar
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a_t_b_delay = self.inv.analytical_delay(slew=slew, load=self.nand.input_load())
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# inbar -> z
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b_t_z_delay = self.nand.analytical_delay(slew=a_t_b_delay.slew, load=self.inv.input_load())
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# Z -> out
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a_t_out_delay = self.inv.analytical_delay(slew=b_t_z_delay.slew, load=load)
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return a_t_b_delay + b_t_z_delay + a_t_out_delay
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def input_load(self):
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return self.nand.input_load()
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