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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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6990773ea16edc06e5e7670fc1ba38bab1a5914f
OpenRAM/compiler/bitcells
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Hunter Nichols a711a5823d Merged dev and fix conflicts in geometry.py
2018-10-24 10:52:22 -07:00
..
bitcell_1rw_1r.py
Fixed lib files to be syntactically correct with multiport. Fixed issue in geometry.py that prevented netlist_only option from working.
2018-10-22 23:33:01 -07:00
bitcell.py
Merge branch 'multiport' into supply_routing
2018-10-11 09:56:38 -07:00
pbitcell.py
Updating comments and cleaning up code for pbitcell.
2018-10-21 19:10:04 -07:00
replica_bitcell.py
Move replica bitcells to new bitcells subdir
2018-10-24 09:06:29 -07:00
replica_pbitcell.py
Move replica bitcells to new bitcells subdir
2018-10-24 09:06:29 -07:00
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