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bank.py
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Removing din and dout list names in exchange for a read index. Write ports will always be in order (they will not skip numbers. Read ports however will skip the numbers assigned to wirte ports so the index of the read ports must be tracked.
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2018-09-09 14:14:26 -07:00 |
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bank_select.py
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Move place function to instance class rather than hierarchy.
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2018-08-27 17:25:39 -07:00 |
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bitcell.py
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Merging latest changes from multiport with changes made to pbitcell. Changing select code from other modules and tests to reflect changes made to pbitcell.
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2018-09-06 19:36:50 -07:00 |
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bitcell_array.py
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Clean up new code for add_modules, add_pins and netlist/layouts.
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2018-08-28 10:24:09 -07:00 |
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control_logic.py
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Move place function to instance class rather than hierarchy.
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2018-08-27 17:25:39 -07:00 |
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delay_chain.py
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Make bitcell width/height not static. Update modules to use it for pbitcell.
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2018-09-04 11:55:22 -07:00 |
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dff.py
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Add dff_buf for buffered flop arrays.
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2018-03-04 16:13:10 -08:00 |
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dff_array.py
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Clean up new code for add_modules, add_pins and netlist/layouts.
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2018-08-28 10:24:09 -07:00 |
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dff_buf.py
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Clean up new code for add_modules, add_pins and netlist/layouts.
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2018-08-28 10:24:09 -07:00 |
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dff_buf_array.py
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Clean up new code for add_modules, add_pins and netlist/layouts.
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2018-08-28 10:24:09 -07:00 |
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dff_inv.py
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Clean up new code for add_modules, add_pins and netlist/layouts.
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2018-08-28 10:24:09 -07:00 |
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dff_inv_array.py
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Found rotate bug in transformCoordinate. Cleaned up transFlags.
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2018-09-04 16:35:40 -07:00 |
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hierarchical_decoder.py
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Make bitcell width/height not static. Update modules to use it for pbitcell.
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2018-09-04 11:55:22 -07:00 |
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hierarchical_predecode.py
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Move place function to instance class rather than hierarchy.
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2018-08-27 17:25:39 -07:00 |
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hierarchical_predecode2x4.py
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Converted all modules to not run create_layout when netlist_only
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2018-08-27 16:42:48 -07:00 |
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hierarchical_predecode3x8.py
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Converted all modules to not run create_layout when netlist_only
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2018-08-27 16:42:48 -07:00 |
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ms_flop.py
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Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.
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2018-03-01 23:34:15 -08:00 |
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ms_flop_array.py
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Clean up new code for add_modules, add_pins and netlist/layouts.
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2018-08-28 10:24:09 -07:00 |
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multibank.py
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Initial refactor of signal and supply router classes.
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2018-08-29 15:34:45 -07:00 |
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precharge_array.py
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Clean up new code for add_modules, add_pins and netlist/layouts.
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2018-08-28 10:24:09 -07:00 |
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replica_bitcell.py
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Finish renaming replica bitcell and bitline pin names.
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2018-09-04 14:03:15 -07:00 |
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replica_bitline.py
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Commiting working version of multi-port that can generate a netlist on the sram level. Changes that will clean up the code are forthcoming.
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2018-09-09 14:00:51 -07:00 |
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sense_amp.py
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Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.
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2018-03-01 23:34:15 -08:00 |
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sense_amp_array.py
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Make bitcell width/height not static. Update modules to use it for pbitcell.
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2018-09-04 11:55:22 -07:00 |
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single_level_column_mux_array.py
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Clean up new code for add_modules, add_pins and netlist/layouts.
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2018-08-28 10:24:09 -07:00 |
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tri_gate.py
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Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.
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2018-03-01 23:34:15 -08:00 |
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tri_gate_array.py
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Clean up new code for add_modules, add_pins and netlist/layouts.
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2018-08-28 10:24:09 -07:00 |
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wordline_driver.py
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Make bitcell width/height not static. Update modules to use it for pbitcell.
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2018-09-04 11:55:22 -07:00 |
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write_driver.py
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Organize top-level files into subdirs.
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2018-02-09 10:25:24 -08:00 |
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write_driver_array.py
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Make bitcell width/height not static. Update modules to use it for pbitcell.
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2018-09-04 11:55:22 -07:00 |
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