mirror of https://github.com/VLSIDA/OpenRAM.git
108 lines
4.3 KiB
Python
Executable File
108 lines
4.3 KiB
Python
Executable File
#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import unittest
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from testutils import *
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import sys, os
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sys.path.append(os.getenv("OPENRAM_HOME"))
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import globals
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from globals import OPTS
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from sram_factory import factory
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import debug
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class timing_sram_test(openram_test):
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def runTest(self):
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config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
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globals.init_openram(config_file)
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OPTS.spice_name="hspice"
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OPTS.analytical_delay = False
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OPTS.netlist_only = True
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# This is a hack to reload the characterizer __init__ with the spice version
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from importlib import reload
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import characterizer
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reload(characterizer)
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from characterizer import delay
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from sram_config import sram_config
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c = sram_config(word_size=1,
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num_words=16,
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num_banks=1)
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c.words_per_row=1
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# c = sram_config(word_size=32,
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# num_words=256,
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# num_banks=1)
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# c.words_per_row=2
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# OPTS.use_tech_delay_chain_size = True
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c.recompute_sizes()
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debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")
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s = factory.create(module_type="sram", sram_config=c)
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#import sys
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#sys.exit(1)
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tempspice = OPTS.openram_temp + "temp.sp"
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s.sp_write(tempspice)
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probe_address = "1" * s.s.addr_size
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probe_data = s.s.word_size - 1
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debug.info(1, "Probe address {0} probe data bit {1}".format(probe_address, probe_data))
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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d = delay(s.s, tempspice, corner)
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import tech
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loads = [tech.spice["dff_in_cap"]*4]
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slews = [tech.spice["rise_time"]*2]
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data, port_data = d.analyze(probe_address, probe_data, slews, loads)
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#Combine info about port into all data
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data.update(port_data[0])
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if OPTS.tech_name == "freepdk45":
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golden_data = {'min_period': 0.898,
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'write1_power': [0.2659137999999999],
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'disabled_write0_power': [0.1782495],
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'disabled_read0_power': [0.14490679999999997],
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'write0_power': [0.3330119],
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'disabled_write1_power': [0.1865223],
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'leakage_power': 0.0014532,
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'disabled_read1_power': [0.1627516],
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'slew_lh': [0.25367799999999996],
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'slew_hl': [0.25367799999999996],
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'delay_lh': [0.23820930000000004],
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'delay_hl': [0.23820930000000004],
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'read1_power': [0.3005756],
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'read0_power': [0.3005888]}
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elif OPTS.tech_name == "scn4m_subm":
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golden_data = {'leakage_power': 0.0006356576000000001,
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'write1_power': [11.292700000000002],
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'read0_power': [12.98],
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'disabled_write1_power': [8.3707],
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'write0_power': [14.4447], 'delay_hl': [1.7445000000000002],
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'disabled_read0_power': [6.4325],
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'slew_hl': [1.7437],
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'disabled_write0_power': [8.1307],
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'slew_lh': [1.7437],
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'read1_power': [12.9869],
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'disabled_read1_power': [7.706],
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'min_period': 6.25,
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'delay_lh': [1.7445000000000002]}
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else:
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self.assertTrue(False) # other techs fail
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# Check if no too many or too few results
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self.assertTrue(len(data.keys())==len(golden_data.keys()))
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self.assertTrue(self.check_golden_data(data,golden_data,0.25))
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globals.end_openram()
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# run the test from the command line
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main(testRunner=debugTestRunner())
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