mirror of https://github.com/VLSIDA/OpenRAM.git
615 lines
23 KiB
Python
615 lines
23 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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"""
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This is called globals.py, but it actually parses all the arguments
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and performs the global OpenRAM setup as well.
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"""
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import os
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import debug
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import shutil
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import optparse
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import options
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import sys
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import re
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import copy
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import importlib
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VERSION = "1.1.6"
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NAME = "OpenRAM v{}".format(VERSION)
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USAGE = "openram.py [options] <config file>\nUse -h for help.\n"
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OPTS = options.options()
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CHECKPOINT_OPTS = None
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def parse_args():
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""" Parse the optional arguments for OpenRAM """
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global OPTS
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option_list = {
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optparse.make_option("-b",
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"--backannotated",
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action="store_true",
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dest="use_pex",
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help="Back annotate simulation"),
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optparse.make_option("-o",
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"--output",
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dest="output_name",
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help="Base output file name(s) prefix",
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metavar="FILE"),
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optparse.make_option("-p", "--outpath",
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dest="output_path",
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help="Output file(s) location"),
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optparse.make_option("-i",
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"--inlinecheck",
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action="store_true",
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help="Enable inline LVS/DRC checks",
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dest="inline_lvsdrc"),
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optparse.make_option("-n", "--nocheck",
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action="store_false",
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help="Disable all LVS/DRC checks",
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dest="check_lvsdrc"),
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optparse.make_option("-j", "--threads",
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action="store",
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type="int",
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help="Specify the number of threads (default: 2)",
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dest="num_threads"),
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optparse.make_option("-v",
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"--verbose",
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action="count",
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dest="verbose_level",
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help="Increase the verbosity level"),
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optparse.make_option("-t",
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"--tech",
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dest="tech_name",
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help="Technology name"),
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optparse.make_option("-s",
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"--spice",
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dest="spice_name",
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help="Spice simulator executable name"),
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optparse.make_option("-r",
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"--remove_netlist_trimming",
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action="store_false",
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dest="trim_netlist",
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help="Disable removal of noncritical memory cells during characterization"),
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optparse.make_option("-c",
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"--characterize",
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action="store_false",
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dest="analytical_delay",
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help="Perform characterization to calculate delays (default is analytical models)"),
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optparse.make_option("-k",
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"--keeptemp",
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action="store_true",
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dest="keep_temp",
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help="Keep the contents of the temp directory after a successful run"),
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optparse.make_option("-d",
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"--debug",
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action="store_true",
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dest="debug",
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help="Run in debug mode to drop to pdb on failure")
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# -h --help is implicit.
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}
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parser = optparse.OptionParser(option_list=option_list,
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description=NAME,
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usage=USAGE,
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version=VERSION)
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(options, args) = parser.parse_args(values=OPTS)
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# If we don't specify a tech, assume scmos.
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# This may be overridden when we read a config file though...
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if OPTS.tech_name == "":
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OPTS.tech_name = "scmos"
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# Alias SCMOS to 180nm
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if OPTS.tech_name == "scmos":
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OPTS.tech_name = "scn4m_subm"
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# Alias s8 to sky130
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if OPTS.tech_name == "s8":
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OPTS.tech_name = "sky130"
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return (options, args)
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def print_banner():
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""" Conditionally print the banner to stdout """
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global OPTS
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if OPTS.is_unit_test:
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return
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debug.print_raw("|==============================================================================|")
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debug.print_raw("|=========" + NAME.center(60) + "=========|")
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debug.print_raw("|=========" + " ".center(60) + "=========|")
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debug.print_raw("|=========" + "VLSI Design and Automation Lab".center(60) + "=========|")
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debug.print_raw("|=========" + "Computer Science and Engineering Department".center(60) + "=========|")
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debug.print_raw("|=========" + "University of California Santa Cruz".center(60) + "=========|")
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debug.print_raw("|=========" + " ".center(60) + "=========|")
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user_info = "Usage help: openram-user-group@ucsc.edu"
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debug.print_raw("|=========" + user_info.center(60) + "=========|")
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dev_info = "Development help: openram-dev-group@ucsc.edu"
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debug.print_raw("|=========" + dev_info.center(60) + "=========|")
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temp_info = "Temp dir: {}".format(OPTS.openram_temp)
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debug.print_raw("|=========" + temp_info.center(60) + "=========|")
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debug.print_raw("|=========" + "See LICENSE for license info".center(60) + "=========|")
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debug.print_raw("|==============================================================================|")
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def check_versions():
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""" Run some checks of required software versions. """
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# Now require python >=3.5
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major_python_version = sys.version_info.major
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minor_python_version = sys.version_info.minor
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major_required = 3
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minor_required = 5
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if not (major_python_version == major_required and minor_python_version >= minor_required):
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debug.error("Python {0}.{1} or greater is required.".format(major_required,minor_required),-1)
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# FIXME: Check versions of other tools here??
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# or, this could be done in each module (e.g. verify, characterizer, etc.)
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global OPTS
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try:
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import coverage
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OPTS.coverage = 1
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except:
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OPTS.coverage = 0
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def init_openram(config_file, is_unit_test=True):
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""" Initialize the technology, paths, simulators, etc. """
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check_versions()
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debug.info(1, "Initializing OpenRAM...")
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setup_paths()
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read_config(config_file, is_unit_test)
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import_tech()
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set_default_corner()
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init_paths()
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from sram_factory import factory
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factory.reset()
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global OPTS
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global CHECKPOINT_OPTS
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# This is a hack. If we are running a unit test and have checkpointed
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# the options, load them rather than reading the config file.
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# This way, the configuration is reloaded at the start of every unit test.
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# If a unit test fails,
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# we don't have to worry about restoring the old config values
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# that may have been tested.
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if is_unit_test and CHECKPOINT_OPTS:
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OPTS.__dict__ = CHECKPOINT_OPTS.__dict__.copy()
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return
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# Setup correct bitcell names
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setup_bitcell()
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# Import these to find the executables for checkpointing
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import characterizer
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import verify
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# Make a checkpoint of the options so we can restore
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# after each unit test
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if not CHECKPOINT_OPTS:
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CHECKPOINT_OPTS = copy.copy(OPTS)
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def setup_bitcell():
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"""
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Determine the correct custom or parameterized bitcell for the design.
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"""
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# If we have non-1rw ports,
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# and the user didn't over-ride the bitcell manually,
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# figure out the right bitcell to use
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if OPTS.bitcell == "bitcell":
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if (OPTS.num_rw_ports == 1 and OPTS.num_w_ports == 0 and OPTS.num_r_ports == 0):
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OPTS.bitcell = "bitcell"
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else:
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ports = ""
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if OPTS.num_rw_ports > 0:
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ports += "{}rw_".format(OPTS.num_rw_ports)
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if OPTS.num_w_ports > 0:
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ports += "{}w_".format(OPTS.num_w_ports)
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if OPTS.num_r_ports > 0:
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ports += "{}r".format(OPTS.num_r_ports)
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if ports != "":
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OPTS.bitcell_suffix = "_" + ports
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OPTS.bitcell = "bitcell" + OPTS.bitcell_suffix
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OPTS.dummy_bitcell = "dummy_" + OPTS.bitcell
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OPTS.replica_bitcell = "replica_" + OPTS.bitcell
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elif OPTS.bitcell == "pbitcell":
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OPTS.bitcell = "pbitcell"
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OPTS.dummy_bitcell = "dummy_pbitcell"
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OPTS.replica_bitcell = "replica_pbitcell"
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# See if bitcell exists
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try:
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__import__(OPTS.bitcell)
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except ImportError:
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# Use the pbitcell if we couldn't find a custom bitcell
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# or its custom replica bitcell
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# Use the pbitcell (and give a warning if not in unit test mode)
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OPTS.bitcell = "pbitcell"
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OPTS.dummy_bitcell = "dummy_pbitcell"
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OPTS.replica_bitcell = "replica_pbitcell"
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if not OPTS.is_unit_test:
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debug.warning("Using the parameterized bitcell which may have suboptimal density.")
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debug.info(1, "Using bitcell: {}".format(OPTS.bitcell))
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def get_tool(tool_type, preferences, default_name=None):
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"""
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Find which tool we have from a list of preferences and return the
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one selected and its full path. If default is specified,
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find that one only and error otherwise.
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"""
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debug.info(2, "Finding {} tool...".format(tool_type))
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if default_name:
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exe_name = find_exe(default_name)
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if exe_name == None:
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debug.error("{0} not found. Cannot find {1} tool.".format(default_name, tool_type)
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+ "Disable DRC/LVS with check_lvsdrc=False to ignore.",
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2)
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else:
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debug.info(1, "Using {0}: {1}".format(tool_type, exe_name))
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return(default_name, exe_name)
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else:
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for name in preferences:
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exe_name = find_exe(name)
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if exe_name != None:
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debug.info(1, "Using {0}: {1}".format(tool_type, exe_name))
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return(name, exe_name)
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else:
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debug.info(1,
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"Could not find {0}, trying next {1} tool.".format(name, tool_type))
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else:
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return(None, "")
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def read_config(config_file, is_unit_test=True):
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"""
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Read the configuration file that defines a few parameters. The
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config file is just a Python file that defines some config
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options. This will only actually get read the first time. Subsequent
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reads will just restore the previous copy (ask mrg)
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"""
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global OPTS
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# it is already not an abs path, make it one
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if not os.path.isabs(config_file):
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config_file = os.getcwd() + "/" + config_file
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# Make it a python file if the base name was only given
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config_file = re.sub(r'\.py$', "", config_file)
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# Expand the user if it is used
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config_file = os.path.expanduser(config_file)
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OPTS.config_file = config_file + ".py"
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# Add the path to the system path
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# so we can import things in the other directory
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dir_name = os.path.dirname(config_file)
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module_name = os.path.basename(config_file)
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# Prepend the path to avoid if we are using the example config
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sys.path.insert(0, dir_name)
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# Import the configuration file of which modules to use
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debug.info(1, "Configuration file is " + config_file + ".py")
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try:
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config = importlib.import_module(module_name)
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except:
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debug.error("Unable to read configuration file: {0}".format(config_file),2)
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OPTS.overridden = {}
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for k, v in config.__dict__.items():
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# The command line will over-ride the config file
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# except in the case of the tech name! This is because the tech name
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# is sometimes used to specify the config file itself (e.g. unit tests)
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# Note that if we re-read a config file, nothing will get read again!
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if k not in OPTS.__dict__ or k == "tech_name":
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OPTS.__dict__[k] = v
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OPTS.overridden[k] = True
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# Massage the output path to be an absolute one
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if not OPTS.output_path.endswith('/'):
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OPTS.output_path += "/"
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if not OPTS.output_path.startswith('/'):
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OPTS.output_path = os.getcwd() + "/" + OPTS.output_path
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debug.info(1, "Output saved in " + OPTS.output_path)
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# Remember if we are running unit tests to reduce output
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OPTS.is_unit_test = is_unit_test
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# If we are only generating a netlist, we can't do DRC/LVS
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if OPTS.netlist_only:
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OPTS.check_lvsdrc = False
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# If config didn't set output name, make a reasonable default.
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if (OPTS.output_name == ""):
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ports = ""
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if OPTS.num_rw_ports > 0:
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ports += "{}rw_".format(OPTS.num_rw_ports)
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if OPTS.num_w_ports > 0:
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ports += "{}w_".format(OPTS.num_w_ports)
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if OPTS.num_r_ports > 0:
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ports += "{}r_".format(OPTS.num_r_ports)
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OPTS.output_name = "sram_{0}b_{1}_{2}{3}".format(OPTS.word_size,
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OPTS.num_words,
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ports,
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OPTS.tech_name)
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def end_openram():
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""" Clean up openram for a proper exit """
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cleanup_paths()
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if OPTS.check_lvsdrc:
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import verify
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verify.print_drc_stats()
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verify.print_lvs_stats()
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verify.print_pex_stats()
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def cleanup_paths():
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"""
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We should clean up the temp directory after execution.
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"""
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global OPTS
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if OPTS.keep_temp:
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debug.info(0,
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"Preserving temp directory: {}".format(OPTS.openram_temp))
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return
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elif os.path.exists(OPTS.openram_temp):
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debug.info(1,
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"Purging temp directory: {}".format(OPTS.openram_temp))
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# This annoyingly means you have to re-cd into
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# the directory each debug iteration
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# shutil.rmtree(OPTS.openram_temp, ignore_errors=True)
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contents = [os.path.join(OPTS.openram_temp, i) for i in os.listdir(OPTS.openram_temp)]
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for i in contents:
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if os.path.isfile(i) or os.path.islink(i):
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os.remove(i)
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else:
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shutil.rmtree(i)
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def setup_paths():
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""" Set up the non-tech related paths. """
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debug.info(2, "Setting up paths...")
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global OPTS
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try:
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OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME"))
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except:
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debug.error("$OPENRAM_HOME is not properly defined.", 1)
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debug.check(os.path.isdir(OPENRAM_HOME),
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"$OPENRAM_HOME does not exist: {0}".format(OPENRAM_HOME))
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# Add all of the subdirs to the python path
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# These subdirs are modules and don't need
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# to be added: characterizer, verify
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subdirlist = [ item for item in os.listdir(OPENRAM_HOME) if os.path.isdir(os.path.join(OPENRAM_HOME, item)) ]
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for subdir in subdirlist:
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full_path = "{0}/{1}".format(OPENRAM_HOME, subdir)
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debug.check(os.path.isdir(full_path),
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"$OPENRAM_HOME/{0} does not exist: {1}".format(subdir, full_path))
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if "__pycache__" not in full_path:
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sys.path.append("{0}".format(full_path))
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if not OPTS.openram_temp.endswith('/'):
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OPTS.openram_temp += "/"
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debug.info(1, "Temporary files saved in " + OPTS.openram_temp)
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def is_exe(fpath):
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""" Return true if the given is an executable file that exists. """
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return os.path.exists(fpath) and os.access(fpath, os.X_OK)
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def find_exe(check_exe):
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"""
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Check if the binary exists in any path dir
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and return the full path.
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"""
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# Check if the preferred spice option exists in the path
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for path in os.environ["PATH"].split(os.pathsep):
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exe = os.path.join(path, check_exe)
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# if it is found, then break and use first version
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if is_exe(exe):
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return exe
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return None
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def init_paths():
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""" Create the temp and output directory if it doesn't exist """
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# make the directory if it doesn't exist
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try:
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debug.info(1,
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"Creating temp directory: {}".format(OPTS.openram_temp))
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os.makedirs(OPTS.openram_temp, 0o750)
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except OSError as e:
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if e.errno == 17: # errno.EEXIST
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os.chmod(OPTS.openram_temp, 0o750)
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# Don't delete the output dir, it may have other files!
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# make the directory if it doesn't exist
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try:
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os.makedirs(OPTS.output_path, 0o750)
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except OSError as e:
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if e.errno == 17: # errno.EEXIST
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os.chmod(OPTS.output_path, 0o750)
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except:
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debug.error("Unable to make output directory.", -1)
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def set_default_corner():
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""" Set the default corner. """
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import tech
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# Set some default options now based on the technology...
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if (OPTS.process_corners == ""):
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if OPTS.nominal_corner_only:
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OPTS.process_corners = ["TT"]
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else:
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OPTS.process_corners = tech.spice["fet_models"].keys()
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if (OPTS.supply_voltages == ""):
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if OPTS.nominal_corner_only:
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OPTS.supply_voltages = [tech.spice["supply_voltages"][1]]
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else:
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OPTS.supply_voltages = tech.spice["supply_voltages"]
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if (OPTS.temperatures == ""):
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if OPTS.nominal_corner_only:
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OPTS.temperatures = [tech.spice["temperatures"][1]]
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else:
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OPTS.temperatures = tech.spice["temperatures"]
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# Load scales are fanout multiples of the DFF input cap
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if (OPTS.load_scales == ""):
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OPTS.load_scales = [0.25, 1, 4]
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# Load scales are fanout multiples of the default spice input slew
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if (OPTS.slew_scales == ""):
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OPTS.slew_scales = [0.25, 1, 8]
|
|
|
|
|
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def import_tech():
|
|
""" Dynamically adds the tech directory to the path and imports it. """
|
|
global OPTS
|
|
|
|
debug.info(2,
|
|
"Importing technology: " + OPTS.tech_name)
|
|
|
|
# environment variable should point to the technology dir
|
|
try:
|
|
OPENRAM_TECH = os.path.abspath(os.environ.get("OPENRAM_TECH"))
|
|
except:
|
|
debug.error("$OPENRAM_TECH environment variable is not defined.", 1)
|
|
|
|
# Add all of the paths
|
|
for tech_path in OPENRAM_TECH.split(":"):
|
|
debug.check(os.path.isdir(tech_path),
|
|
"$OPENRAM_TECH does not exist: {0}".format(tech_path))
|
|
sys.path.append(tech_path)
|
|
debug.info(1, "Adding technology path: {}".format(tech_path))
|
|
|
|
# Import the tech
|
|
try:
|
|
tech_mod = __import__(OPTS.tech_name)
|
|
except ImportError:
|
|
debug.error("Nonexistent technology module: {0}".format(OPTS.tech_name), -1)
|
|
|
|
OPTS.openram_tech = os.path.dirname(tech_mod.__file__) + "/"
|
|
|
|
# Add the tech directory
|
|
tech_path = OPTS.openram_tech
|
|
sys.path.append(tech_path)
|
|
try:
|
|
import tech
|
|
except ImportError:
|
|
debug.error("Could not load tech module.", -1)
|
|
|
|
# Add custom modules of the technology to the path, if they exist
|
|
custom_mod_path = os.path.join(tech_path, "modules/")
|
|
if os.path.exists(custom_mod_path):
|
|
sys.path.append(custom_mod_path)
|
|
|
|
|
|
def print_time(name, now_time, last_time=None, indentation=2):
|
|
""" Print a statement about the time delta. """
|
|
global OPTS
|
|
|
|
# Don't print during testing
|
|
if not OPTS.is_unit_test or OPTS.verbose_level > 0:
|
|
if last_time:
|
|
time = str(round((now_time - last_time).total_seconds(), 1)) + " seconds"
|
|
else:
|
|
time = now_time.strftime('%m/%d/%Y %H:%M:%S')
|
|
debug.print_raw("{0} {1}: {2}".format("*" * indentation, name, time))
|
|
|
|
|
|
def report_status():
|
|
"""
|
|
Check for valid arguments and report the
|
|
info about the SRAM being generated
|
|
"""
|
|
global OPTS
|
|
|
|
# Check if all arguments are integers for bits, size, banks
|
|
if type(OPTS.word_size) != int:
|
|
debug.error("{0} is not an integer in config file.".format(OPTS.word_size))
|
|
if type(OPTS.num_words) != int:
|
|
debug.error("{0} is not an integer in config file.".format(OPTS.sram_size))
|
|
if type(OPTS.write_size) is not int and OPTS.write_size is not None:
|
|
debug.error("{0} is not an integer in config file.".format(OPTS.write_size))
|
|
|
|
# If a write mask is specified by the user, the mask write size should be the same as
|
|
# the word size so that an entire word is written at once.
|
|
if OPTS.write_size is not None:
|
|
if (OPTS.word_size % OPTS.write_size != 0):
|
|
debug.error("Write size needs to be an integer multiple of word size.")
|
|
# If write size is more than half of the word size,
|
|
# then it doesn't need a write mask. It would be writing
|
|
# the whole word.
|
|
if (OPTS.write_size < 1 or OPTS.write_size > OPTS.word_size/2):
|
|
debug.error("Write size needs to be between 1 bit and {0} bits/2.".format(OPTS.word_size))
|
|
|
|
if not OPTS.tech_name:
|
|
debug.error("Tech name must be specified in config file.")
|
|
|
|
debug.print_raw("Technology: {0}".format(OPTS.tech_name))
|
|
total_size = OPTS.word_size*OPTS.num_words*OPTS.num_banks
|
|
debug.print_raw("Total size: {} bits".format(total_size))
|
|
if total_size >= 2**14:
|
|
debug.warning("Requesting such a large memory size ({0}) will have a large run-time. ".format(total_size) +
|
|
"Consider using multiple smaller banks.")
|
|
debug.print_raw("Word size: {0}\nWords: {1}\nBanks: {2}".format(OPTS.word_size,
|
|
OPTS.num_words,
|
|
OPTS.num_banks))
|
|
if (OPTS.write_size != OPTS.word_size):
|
|
debug.print_raw("Write size: {}".format(OPTS.write_size))
|
|
debug.print_raw("RW ports: {0}\nR-only ports: {1}\nW-only ports: {2}".format(OPTS.num_rw_ports,
|
|
OPTS.num_r_ports,
|
|
OPTS.num_w_ports))
|
|
|
|
if OPTS.netlist_only:
|
|
debug.print_raw("Netlist only mode (no physical design is being done, netlist_only=False to disable).")
|
|
|
|
if not OPTS.route_supplies:
|
|
debug.print_raw("Design supply routing skipped. Supplies will have multiple must-connect pins. (route_supplies=True to enable supply routing).")
|
|
|
|
if not OPTS.inline_lvsdrc:
|
|
debug.print_raw("DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).")
|
|
|
|
if not OPTS.check_lvsdrc:
|
|
debug.print_raw("DRC/LVS/PEX is disabled (check_lvsdrc=True to enable).")
|
|
|
|
if OPTS.analytical_delay:
|
|
debug.print_raw("Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate).")
|
|
else:
|
|
if OPTS.spice_name != "":
|
|
debug.print_raw("Performing simulation-based characterization with {}".format(OPTS.spice_name))
|
|
if OPTS.trim_netlist:
|
|
debug.print_raw("Trimming netlist to speed up characterization (trim_netlist=False to disable).")
|
|
if OPTS.nominal_corner_only:
|
|
debug.print_raw("Only generating nominal corner timing.")
|