mirror of https://github.com/VLSIDA/OpenRAM.git
59 lines
2.0 KiB
Python
59 lines
2.0 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import debug
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import design
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import utils
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from tech import GDS, layer
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class tri_gate(design.design):
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"""
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This module implements the tri gate cell used in the design forS
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bit-line isolation. It is a hand-made cell, so the layout and
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netlist should be available in the technology library.
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"""
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pin_names = ["in", "out", "en", "en_bar", "vdd", "gnd"]
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type_list = ["INPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"]
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cell_size_layer = "boundary"
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unique_id = 1
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def __init__(self, name=""):
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if name=="":
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name = "tri{0}".format(tri_gate.unique_id)
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tri_gate.unique_id += 1
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super().__init__(self, name)
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debug.info(2, "Create tri_gate")
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(width, height) = utils.get_libcell_size(self.cell_name,
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GDS["unit"],
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layer[self.cell_size_layer])
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pin_map = utils.get_libcell_pins(self.pin_names,
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self.cell_name,
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GDS["unit"])
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self.width = width
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self.height = height
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self.pin_map = pin_map
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self.add_pin_types(self.type_list)
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def analytical_power(self, corner, load):
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"""Returns dynamic and leakage power. Results in nW"""
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#Power in this module currently not defined. Returns 0 nW (leakage and dynamic).
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total_power = self.return_power()
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return total_power
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def get_cin(self):
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return 9*spice["min_tx_gate_c"]
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def build_graph(self, graph, inst_name, port_nets):
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"""Adds edges based on inputs/outputs. Overrides base class function."""
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self.add_graph_edges(graph, port_nets)
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