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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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676b6764c7011e4f8647c8a7538ef2252bbcbb8b
OpenRAM/compiler/pgates
T
History
Hunter Nichols 5dfa8bc2c6 Fixed known typos of the word transition.
2018-09-10 14:27:26 -07:00
..
pbitcell.py
Make bitcell width/height not static. Update modules to use it for pbitcell.
2018-09-04 11:55:22 -07:00
pgate.py
Make bitcell width/height not static. Update modules to use it for pbitcell.
2018-09-04 11:55:22 -07:00
pinv.py
Fixed known typos of the word transition.
2018-09-10 14:27:26 -07:00
pinvbuf.py
Make bitcell width/height not static. Update modules to use it for pbitcell.
2018-09-04 11:55:22 -07:00
pnand2.py
Fixed known typos of the word transition.
2018-09-10 14:27:26 -07:00
pnand3.py
Fixed known typos of the word transition.
2018-09-10 14:27:26 -07:00
pnor2.py
Fixed known typos of the word transition.
2018-09-10 14:27:26 -07:00
precharge.py
Move place function to instance class rather than hierarchy.
2018-08-27 17:25:39 -07:00
ptx.py
Converted all modules to not run create_layout when netlist_only
2018-08-27 16:42:48 -07:00
single_level_column_mux.py
Make bitcell width/height not static. Update modules to use it for pbitcell.
2018-09-04 11:55:22 -07:00
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