Logo
Explore Help
Sign In
luke/OpenRAM
Watch 1
Star 0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-30 09:58:33 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
66b2fcdc91401e553ac494853f0b50b3dfe0f36a
OpenRAM/compiler/pgates
T
History
Hunter Nichols 8eb4812e16 Made parasitic delay parameter in Freepdk45 more accurate, added stage names to delay model.
2018-12-17 23:32:02 -08:00
..
pand2.py
Changed s_en delay calculation based recent control logic changes.
2018-12-05 17:10:11 -08:00
pbuf.py
Changed s_en delay calculation based recent control logic changes.
2018-12-05 17:10:11 -08:00
pdriver.py
Passed freepdk45 tests with pdriver.py
2018-12-07 12:58:05 -08:00
pgate.py
Update all drc usages to call function type
2018-10-12 14:37:51 -07:00
pinv.py
Made parasitic delay parameter in Freepdk45 more accurate, added stage names to delay model.
2018-12-17 23:32:02 -08:00
pinvbuf.py
Separated relative delay into rise/fall.
2018-11-14 23:34:53 -08:00
pnand2.py
Made parasitic delay parameter in Freepdk45 more accurate, added stage names to delay model.
2018-12-17 23:32:02 -08:00
pnand3.py
Made parasitic delay parameter in Freepdk45 more accurate, added stage names to delay model.
2018-12-17 23:32:02 -08:00
pnor2.py
Update all drc usages to call function type
2018-10-12 14:37:51 -07:00
precharge.py
Merged with dev. Fixed conflicts in tests.
2018-12-02 23:09:00 -08:00
ptx.py
Merged with dev. Fixed conflicts in tests.
2018-12-02 23:09:00 -08:00
single_level_column_mux.py
Merge branch 'dev' into multiport_layout
2018-11-08 18:00:28 -08:00
Powered by Gitea Version: 1.27.2 Page: 47ms Template: 2ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API