mirror of https://github.com/VLSIDA/OpenRAM.git
139 lines
6.0 KiB
Python
139 lines
6.0 KiB
Python
#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2023 Regents of the University of California
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# All rights reserved.
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#
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from openram import debug
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from openram.base import geometry
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from openram.sram_factory import factory
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from openram.tech import layer
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from openram import OPTS
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from .sky130_bitcell_base_array import sky130_bitcell_base_array
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from openram.modules import pattern
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class sky130_replica_column(sky130_bitcell_base_array):
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"""
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Generate a replica bitline column for the replica array.
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Rows is the total number of rows i the main array.
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rbl is a tuple with the number of left and right replica bitlines.
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Replica bit specifies which replica column this is (to determine where to put the
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replica cell relative to the bottom (including the dummy bit at 0).
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"""
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def __init__(self, name, rows, rbl, replica_bit, column_offset=0):
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# Used for pin names and properties
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self.cell = factory.create(module_type=OPTS.bitcell)
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# Row size is the number of rows with word lines
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self.row_size = sum(rbl) + rows
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# Start of regular word line rows
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self.row_start = rbl[0]
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# End of regular word line rows
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self.row_end = self.row_start + rows
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super().__init__(rows=self.row_size, cols=1, column_offset=column_offset, name=name)
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self.rows = rows
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self.left_rbl = rbl[0]
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self.right_rbl = rbl[1]
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self.replica_bit = replica_bit
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# left, right, regular rows plus top/bottom dummy cells
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self.total_size = self.left_rbl + rows + self.right_rbl
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self.column_offset = column_offset
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# if self.rows % 2 == 0:
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# debug.error("Invalid number of rows {}. Number of rows must be even to connect to col ends".format(self.rows), -1)
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# if self.column_offset % 2 == 0:
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# debug.error("Invalid column_offset {}. Column offset must be odd to connect to col ends".format(self.rows), -1)
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# debug.check(replica_bit != 0 and replica_bit != rows,
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# "Replica bit cannot be the dummy row.")
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# debug.check(replica_bit <= self.left_rbl or replica_bit >= self.total_size - self.right_rbl - 1,
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# "Replica bit cannot be in the regular array.")
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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self.add_modules()
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self.add_pins()
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self.create_instances()
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def create_layout(self):
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self.place_array()
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self.add_layout_pins()
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self.route_supplies()
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self.add_boundary()
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self.DRC_LVS()
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def add_pins(self):
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self.create_all_bitline_names()
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#self.create_all_wordline_names(self.row_size+2)
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# +2 to add fake wl pins for colends
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self.create_all_wordline_names(self.row_size)
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self.add_pin_list(self.all_bitline_names, "OUTPUT")
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self.add_pin_list(self.all_wordline_names, "INPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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#self.add_pin("top_gate", "INPUT")
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#self.add_pin("bot_gate", "INPUT")
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def add_modules(self):
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self.replica_cell = factory.create(module_type="replica_bitcell_1port", version="opt1")
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self.cell = self.replica_cell
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self.replica_cell2 = factory.create(module_type="replica_bitcell_1port", version="opt1a")
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self.dummy_cell = factory.create(module_type="dummy_bitcell_1port", version="opt1")
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self.dummy_cell2 = factory.create(module_type="dummy_bitcell_1port", version="opt1")
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self.strap = factory.create(module_type="internal", version="wlstrap_p")
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self.strap2 = factory.create(module_type="internal", version="wlstrapa_p")
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def create_instances(self):
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""" Create the module instances used in this design """
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self.all_inst={}
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self.cell_inst={}
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replica_row_opt1 = [geometry.instance("00_rep_opt1", mod=self.replica_cell, is_bitcell=True, mirror='XY')] \
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+ [geometry.instance("01_strap1", mod=self.strap, is_bitcell=False, mirror='MX')]
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replica_row_opt1a = [geometry.instance("10_opt1a", mod=self.replica_cell2, is_bitcell=True, mirror='MY')] \
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+ [geometry.instance("11_strapa", mod=self.strap2, is_bitcell=False)]
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replica_dummy_row_opt1 = [geometry.instance("00_rep_opt1", mod=self.dummy_cell, is_bitcell=True, mirror='MX')] \
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+ [geometry.instance("01_rep_strap", mod=self.strap, is_bitcell=False, mirror='MX')]
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replica_dummy_row_opt1a = [geometry.instance("10_opt1a", mod=self.dummy_cell2, is_bitcell=True, mirror='MY')] \
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+ [geometry.instance("11_strapa", mod=self.strap2, is_bitcell=False)]
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bit_block = []
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current_row = self.row_start
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for row in range(self.total_size):
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# Regular array cells are replica cells
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# Replic bit specifies which other bit (in the full range (0,total_size) to make a replica cell.
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# All other cells are dummies
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if (row == self.replica_bit) or (row >= self.row_start and row < self.row_end):
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if current_row % 2:
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pattern.append_row_to_block(bit_block, replica_row_opt1)
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else:
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pattern.append_row_to_block(bit_block, replica_row_opt1a)
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else:
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if current_row %2:
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pattern.append_row_to_block(bit_block, replica_dummy_row_opt1)
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else:
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pattern.append_row_to_block(bit_block, replica_dummy_row_opt1a)
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current_row += 1
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self.pattern = pattern(self, "replica_column", bit_block, num_rows=self.total_size, num_cols=len(replica_row_opt1a), name_template="rbc_r{0}_c{1}", )
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self.pattern.connect_array_raw()
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def exclude_all_but_replica(self):
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"""
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Excludes all bits except the replica cell (self.replica_bit).
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"""
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for row, cell in self.cell_inst.items():
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if row != self.replica_bit:
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self.graph_inst_exclude.add(cell)
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