mirror of https://github.com/VLSIDA/OpenRAM.git
373 lines
18 KiB
Python
373 lines
18 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import sys,re,shutil
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from design import design
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import debug
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import math
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import tech
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import random
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from .stimuli import *
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from .charutils import *
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import utils
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from globals import OPTS
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from .simulation import simulation
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from .delay import delay
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class functional(simulation):
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"""
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Functions to write random data values to a random address then read them back and check
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for successful SRAM operation.
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"""
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def __init__(self, sram, spfile, corner):
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simulation.__init__(self, sram, spfile, corner)
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# Seed the characterizer with a constant seed for unit tests
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if OPTS.is_unit_test:
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random.seed(687234)
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if self.write_size is not None:
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self.num_wmasks = int(self.word_size / self.write_size)
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else:
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self.num_wmasks = 0
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self.set_corner(corner)
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self.set_spice_constants()
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#self.set_feasible_period(sram, spfile, corner)
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self.set_stimulus_variables()
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self.create_signal_names()
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self.initialize_wmask()
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# Number of checks can be changed
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self.num_cycles = 2
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self.stored_words = {}
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self.write_check = []
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self.read_check = []
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def initialize_wmask(self):
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#self.wmask = [None]*self.num_wmasks
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self.wmask = ""
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if self.write_size is not None:
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# initialize all wmask bits to 1
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for bit in range(self.num_wmasks):
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self.wmask += "1"
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def run(self, feasible_period=None):
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if feasible_period: #period defaults to tech.py feasible period otherwise.
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self.period = feasible_period
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# Generate a random sequence of reads and writes
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self.write_random_memory_sequence()
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# Run SPICE simulation
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self.write_functional_stimulus()
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self.stim.run_sim()
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# read DOUT values from SPICE simulation. If the values do not fall within the noise margins, return the error.
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(success, error) = self.read_stim_results()
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if not success:
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return (0, error)
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# Check read values with written values. If the values do not match, return an error.
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return self.check_stim_results()
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def write_random_memory_sequence(self):
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if self.write_size is not None:
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rw_ops = ["noop", "write", "partial_write", "read"]
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w_ops = ["noop", "write", "partial_write"]
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else:
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rw_ops = ["noop", "write", "read"]
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w_ops = ["noop", "write"]
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r_ops = ["noop", "read"]
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rw_read_din_data = "0"*self.word_size
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check = 0
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# First cycle idle
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comment = self.gen_cycle_comment("noop", "0"*self.word_size, "0"*self.addr_size, self.wmask, 0, self.t_current)
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self.add_noop_all_ports(comment, "0"*self.addr_size, "0"*self.word_size, "0"*self.num_wmasks)
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# Write at least once
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addr = self.gen_addr()
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word = self.gen_data()
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# print("write", self.t_current, addr, word)
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comment = self.gen_cycle_comment("write", word, addr, self.wmask, 0, self.t_current)
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self.add_write(comment, addr, word, self.wmask, 0)
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self.stored_words[addr] = word
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# Read at least once. For multiport, it is important that one read cycle uses all RW and R port to read from the same address simultaniously.
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# This will test the viablilty of the transistor sizing in the bitcell.
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for port in self.all_ports:
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if port in self.write_ports:
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self.add_noop_one_port("0"*self.addr_size, "0"*self.word_size, "0"*self.num_wmasks, port)
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else:
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# print("read", self.t_current, addr, word)
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comment = self.gen_cycle_comment("read", word, addr, self.wmask, port, self.t_current)
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self.add_read_one_port(comment, addr, rw_read_din_data, "1"*self.num_wmasks, port)
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self.write_check.append([word, "{0}{1}".format(self.dout_name,port), self.t_current+self.period, check])
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check += 1
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self.cycle_times.append(self.t_current)
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self.t_current += self.period
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# Perform a random sequence of writes and reads on random ports, using random addresses and random words
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# and random write masks (if applicable)
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for i in range(self.num_cycles):
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w_addrs = []
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for port in self.all_ports:
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if port in self.readwrite_ports:
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op = random.choice(rw_ops)
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elif port in self.write_ports:
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op = random.choice(w_ops)
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else:
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op = random.choice(r_ops)
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if op == "noop":
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addr = "0"*self.addr_size
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word = "0"*self.word_size
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wmask = "0" * self.num_wmasks
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self.add_noop_one_port(addr, word, wmask, port)
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elif op == "write":
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addr = self.gen_addr()
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word = self.gen_data()
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# print("write",self.t_current,addr,word)
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# two ports cannot write to the same address
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if addr in w_addrs:
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self.add_noop_one_port("0"*self.addr_size, "0"*self.word_size, "0"*self.num_wmasks, port)
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else:
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comment = self.gen_cycle_comment("write", word, addr, self.wmask, port, self.t_current)
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self.add_write_one_port(comment, addr, word, self.wmask, port)
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self.stored_words[addr] = word
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w_addrs.append(addr)
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elif op == "partial_write":
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#write only to a word that's been written to
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(addr,old_word) = self.get_data()
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word = self.gen_data()
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wmask = self.gen_wmask()
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new_word = word
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for bit in range(len(wmask)):
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# AWhen the write mask's bits are 0, the old data values should appear in the new word
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if wmask[bit] == "0":
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lower = bit * self.write_size
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upper = lower + self.write_size - 1
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new_word = new_word[:lower] + old_word[lower:upper+1] + new_word[upper + 1:]
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# print("partial_w",self.t_current,addr,wmask,word, "partial_w_word:", new_word)
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# two ports cannot write to the same address
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if addr in w_addrs:
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self.add_noop_one_port("0"*self.addr_size, "0"*self.word_size, "0"*self.num_wmasks, port)
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else:
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comment = self.gen_cycle_comment("partial_write", word, addr, wmask, port, self.t_current)
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self.add_write_one_port(comment, addr, word, wmask, port)
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self.stored_words[addr] = new_word
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w_addrs.append(addr)
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else:
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(addr,word) = random.choice(list(self.stored_words.items()))
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# print("read",self.t_current,addr,word)
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# cannot read from an address that is currently being written to
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if addr in w_addrs:
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self.add_noop_one_port("0"*self.addr_size, "0"*self.word_size, "0"*self.num_wmasks, port)
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else:
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comment = self.gen_cycle_comment("read", word, addr, self.wmask, port, self.t_current)
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self.add_read_one_port(comment, addr, rw_read_din_data, "1"*self.num_wmasks, port)
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self.write_check.append([word, "{0}{1}".format(self.dout_name,port), self.t_current+self.period, check])
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check += 1
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self.cycle_times.append(self.t_current)
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self.t_current += self.period
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# Last cycle idle needed to correctly measure the value on the second to last clock edge
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comment = self.gen_cycle_comment("noop", "0"*self.word_size, "0"*self.addr_size, self.wmask, 0, self.t_current)
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self.add_noop_all_ports(comment, "0"*self.addr_size, "0"*self.word_size, "0"*self.num_wmasks)
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def read_stim_results(self):
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# Extrat DOUT values from spice timing.lis
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for (word, dout_port, eo_period, check) in self.write_check:
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sp_read_value = ""
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for bit in range(self.word_size):
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value = parse_spice_list("timing", "v{0}.{1}ck{2}".format(dout_port.lower(),bit,check))
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if value > self.v_high:
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sp_read_value = "1" + sp_read_value
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elif value < self.v_low:
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sp_read_value = "0" + sp_read_value
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else:
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error ="FAILED: {0}_{1} value {2} at time {3}n does not fall within noise margins <{4} or >{5}.".format(dout_port,
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bit,
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value,
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eo_period,
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self.v_low,
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self.v_high)
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return (0, error)
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self.read_check.append([sp_read_value, dout_port, eo_period, check])
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return (1, "SUCCESS")
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def check_stim_results(self):
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for i in range(len(self.write_check)):
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if self.write_check[i][0] != self.read_check[i][0]:
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error = "FAILED: {0} value {1} does not match written value {2} read during cycle {3} at time {4}n".format(self.read_check[i][1],
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self.read_check[i][0],
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self.write_check[i][0],
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int((self.read_check[i][2]-self.period)/self.period),
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self.read_check[i][2])
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return(0, error)
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return(1, "SUCCESS")
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def gen_wmask(self):
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wmask = ""
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# generate a random wmask
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for bit in range(self.num_wmasks):
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rand = random.randint(0, 1)
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wmask += str(rand)
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# prevent the wmask from having all bits on or off (not partial write)
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all_zeroes = True
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all_ones = True
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for bit in range(self.num_wmasks):
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if wmask[bit]=="0":
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all_ones = False
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elif wmask[bit]=="1":
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all_zeroes = False
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if all_zeroes:
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index = random.randint(0, self.num_wmasks - 1)
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wmask = wmask[:index] + "1" + wmask[index + 1:]
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elif all_ones:
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index = random.randint(0, self.num_wmasks - 1)
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wmask = wmask[:index] + "0" + wmask[index + 1:]
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# wmask must be reversed since a python list goes right to left and sram bits go left to right.
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return wmask[::-1]
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def gen_data(self):
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""" Generates a random word to write. """
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rand = random.randint(0,(2**self.word_size)-1)
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data_bits = self.convert_to_bin(rand,False)
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return data_bits
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# def gen_data(self):
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# """ Generates a random word, either all 0 or all 1's, to write. """
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# rand = random.randint(0,1)
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# bits = []
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# for bit in range(self.word_size):
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# bits.append(rand)
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# data_bits = ''.join(map(str,bits))
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# return data_bits
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def gen_addr(self):
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""" Generates a random address value to write to. """
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rand = random.randint(0,(2**self.addr_size)-1)
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addr_bits = self.convert_to_bin(rand,True)
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return addr_bits
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def get_data(self):
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""" Gets an available address and corresponding word. """
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# Currently unused but may need later depending on how the functional test develops
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addr = random.choice(list(self.stored_words.keys()))
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word = self.stored_words[addr]
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return (addr,word)
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def convert_to_bin(self,value,is_addr):
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""" Converts addr & word to usable binary values. """
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new_value = str.replace(bin(value),"0b","")
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if(is_addr):
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expected_value = self.addr_size
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else:
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expected_value = self.word_size
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for i in range (expected_value - len(new_value)):
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new_value = "0" + new_value
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#print("Binary Conversion: {} to {}".format(value, new_value))
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return new_value
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def write_functional_stimulus(self):
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""" Writes SPICE stimulus. """
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temp_stim = "{0}/stim.sp".format(OPTS.openram_temp)
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self.sf = open(temp_stim,"w")
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self.sf.write("* Functional test stimulus file for {}ns period\n\n".format(self.period))
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self.stim = stimuli(self.sf,self.corner)
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#Write include statements
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self.sram_sp_file = "{}sram.sp".format(OPTS.openram_temp)
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shutil.copy(self.sp_file, self.sram_sp_file)
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self.stim.write_include(self.sram_sp_file)
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#Write Vdd/Gnd statements
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self.sf.write("\n* Global Power Supplies\n")
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self.stim.write_supply()
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#Instantiate the SRAM
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self.sf.write("\n* Instantiation of the SRAM\n")
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self.stim.inst_model(pins=self.pins,
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model_name=self.sram.name)
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# Add load capacitance to each of the read ports
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self.sf.write("\n* SRAM output loads\n")
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for port in self.read_ports:
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for bit in range(self.word_size):
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sig_name="{0}{1}_{2} ".format(self.dout_name, port, bit)
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self.sf.write("CD{0}{1} {2} 0 {3}f\n".format(port, bit, sig_name, self.load))
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# Write debug comments to stim file
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self.sf.write("\n\n * Sequence of operations\n")
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for comment in self.fn_cycle_comments:
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self.sf.write("*{}\n".format(comment))
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# Generate data input bits
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self.sf.write("\n* Generation of data and address signals\n")
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for port in self.write_ports:
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for bit in range(self.word_size):
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sig_name="{0}{1}_{2} ".format(self.din_name, port, bit)
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self.stim.gen_pwl(sig_name, self.cycle_times, self.data_values[port][bit], self.period, self.slew, 0.05)
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# Generate address bits
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for port in self.all_ports:
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for bit in range(self.addr_size):
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sig_name="{0}{1}_{2} ".format(self.addr_name, port, bit)
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self.stim.gen_pwl(sig_name, self.cycle_times, self.addr_values[port][bit], self.period, self.slew, 0.05)
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# Generate control signals
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self.sf.write("\n * Generation of control signals\n")
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for port in self.all_ports:
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self.stim.gen_pwl("CSB{}".format(port), self.cycle_times , self.csb_values[port], self.period, self.slew, 0.05)
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for port in self.readwrite_ports:
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self.stim.gen_pwl("WEB{}".format(port), self.cycle_times , self.web_values[port], self.period, self.slew, 0.05)
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# Generate wmask bits
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for port in self.write_ports:
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if self.write_size is not None:
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self.sf.write("\n* Generation of wmask signals\n")
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for bit in range(self.num_wmasks):
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sig_name = "WMASK{0}_{1} ".format(port, bit)
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# self.stim.gen_pwl(sig_name, self.cycle_times, self.data_values[port][bit], self.period,
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# self.slew, 0.05)
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self.stim.gen_pwl(sig_name, self.cycle_times, self.wmask_values[port][bit], self.period,
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self.slew, 0.05)
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# Generate CLK signals
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for port in self.all_ports:
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self.stim.gen_pulse(sig_name="{0}{1}".format(tech.spice["clk"], port),
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v1=self.gnd_voltage,
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v2=self.vdd_voltage,
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offset=self.period,
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period=self.period,
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t_rise=self.slew,
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t_fall=self.slew)
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# Generate DOUT value measurements
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self.sf.write("\n * Generation of dout measurements\n")
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for (word, dout_port, eo_period, check) in self.write_check:
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t_intital = eo_period - 0.01*self.period
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t_final = eo_period + 0.01*self.period
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for bit in range(self.word_size):
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self.stim.gen_meas_value(meas_name="V{0}_{1}ck{2}".format(dout_port,bit,check),
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dout="{0}_{1}".format(dout_port,bit),
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t_intital=t_intital,
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t_final=t_final)
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self.stim.write_control(self.cycle_times[-1] + self.period)
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self.sf.close()
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