mirror of https://github.com/VLSIDA/OpenRAM.git
47 lines
1.4 KiB
Python
47 lines
1.4 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2023 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from openram import debug
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from openram.base import design
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from openram.tech import cell_properties as props
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class write_driver(design):
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"""
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Tristate write driver to be active during write operations only.
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This module implements the write driver cell used in the design. It
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is a hand-made cell, so the layout and netlist should be available in
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the technology library.
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"""
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def __init__(self, name):
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super().__init__(name, prop=props.write_driver)
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debug.info(2, "Create write_driver")
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def get_bl_names(self):
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return "bl"
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def get_br_names(self):
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return "br"
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@property
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def din_name(self):
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return "din"
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@property
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def en_name(self):
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return "en"
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def get_w_en_cin(self):
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"""Get the relative capacitance of a single input"""
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# This is approximated from SCMOS. It has roughly 5 3x transistor gates.
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return 5 * 3
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def build_graph(self, graph, inst_name, port_nets):
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"""Adds edges based on inputs/outputs. Overrides base class function."""
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self.add_graph_edges(graph, port_nets)
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