mirror of https://github.com/VLSIDA/OpenRAM.git
118 lines
4.9 KiB
Python
118 lines
4.9 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
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# All rights reserved.
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#
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from openram.sram_factory import factory
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from openram import OPTS
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from .bitcell_base_array import bitcell_base_array
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from .pattern import pattern
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from openram.base import geometry
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from math import ceil
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class row_cap_array(bitcell_base_array):
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"""
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Generate a dummy row/column for the replica array.
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"""
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def __init__(self, rows, cols, column_offset=0, row_offset=0, mirror=0, location="", name=""):
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super().__init__(rows=rows, cols=cols, column_offset=column_offset, name=name)
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self.mirror = mirror
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self.location = location
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self.row_offset = row_offset
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#self.no_instances = True
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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""" Create and connect the netlist """
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# This will create a default set of bitline/wordline names
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self.create_all_wordline_names()
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self.create_all_bitline_names()
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self.add_modules()
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self.add_pins()
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self.create_instances()
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def create_layout(self):
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self.place_array()
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self.add_layout_pins()
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self.width = max([x.rx() for x in self.insts])
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self.height = max([x.uy() for x in self.insts])
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self.add_boundary()
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self.DRC_LVS()
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def add_modules(self):
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""" Add the modules used in this design """
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self.row_cap = factory.create(module_type="row_cap_{}".format(OPTS.bitcell))
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self.cell = factory.create(module_type=OPTS.bitcell)
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def create_instances(self):
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""" Create the module instances used in this design """
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self.all_inst={}
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self.cell_inst={}
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bit_block = []
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if self.location == "left":
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#top_corner = geometry.instance("row_cap_top_corner", mod=self.top_corner, is_bitcell=False, mirror="MY")
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#bottom_corner = geometry.instance("row_cap_bottom_corner", mod=self.bottom_corner, is_bitcell=False, mirror="XY")
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rowend = geometry.instance("row_cap_rowend", mod=self.row_cap, is_bitcell=True, mirror="")
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rowend_m = geometry.instance("row_cap_rowend_m", mod=self.row_cap, is_bitcell=True, mirror="MX")
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elif self.location == "right":
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#top_corner = geometry.instance("row_cap_top_corner", mod=self.top_corner, is_bitcell=False)
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#bottom_corner = geometry.instance("row_cap_bottom_corner", mod=self.bottom_corner, is_bitcell=False, mirror="MX")
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rowend = geometry.instance("row_cap_rowend", mod=self.row_cap, is_bitcell=True, mirror="MY")
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rowend_m = geometry.instance("row_cap_rowend_m", mod=self.row_cap, is_bitcell=True, mirror="XY")
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#pattern.append_row_to_block(bit_block, [top_corner])
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for row in range(0, self.row_size):
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if row % 2 == 1:
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pattern.append_row_to_block(bit_block, [rowend])
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else:
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pattern.append_row_to_block(bit_block, [rowend_m])
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#pattern.append_row_to_block(bit_block, [bottom_corner])
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self.pattern = pattern(self, "row_cap_array_" + self.location, bit_block, num_rows=self.row_size, num_cols=self.column_size, num_cores_x=ceil(self.column_size/2), num_cores_y=ceil(self.row_size/2), name_template="row_cap_array" + self.location + "_r{0}_c{1}")
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self.pattern.connect_array_raw()
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def get_bitcell_pins(self, row, col):
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"""
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Creates a list of connections in the bitcell,
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indexed by column and row, for instance use in bitcell_array
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"""
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bitcell_pins = ["wl0_{0}".format(row),
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"wl1_{0}".format(row),
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"gnd"]
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return bitcell_pins
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def add_layout_pins(self):
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""" Add the layout pins """
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wl_names = self.cell.get_all_wl_names()
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max_row = self.row_size - 2
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for row in range(0, max_row):
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for port in self.all_ports:
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wl_pin = self.cell_inst[max_row - 1 - row, 0].get_pin(wl_names[port])
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self.add_layout_pin(text="wl_{0}_{1}".format(port, row),
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layer=wl_pin.layer,
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offset=wl_pin.ll().scale(0, 1),
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width=self.width,
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height=wl_pin.height())
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for row in range(0, max_row):
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for col in range(self.column_size):
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inst = self.cell_inst[row, col]
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for pin_name in ["vdd", "gnd"]:
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for pin in inst.get_pins(pin_name):
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self.add_layout_pin(text=pin_name,
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layer=pin.layer,
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offset=pin.ll(),
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width=pin.width(),
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height=pin.height())
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