mirror of https://github.com/VLSIDA/OpenRAM.git
143 lines
5.4 KiB
Python
143 lines
5.4 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
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# All rights reserved.
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#
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from openram import debug
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from openram.base import vector
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from openram.sram_factory import factory
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from openram.tech import layer_properties as layer_props
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from openram import OPTS
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from .bitcell_base_array import bitcell_base_array
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from openram.base import geometry
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from openram.modules import pattern
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class replica_column(bitcell_base_array):
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"""
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Generate a replica bitline column for the replica array.
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Rows is the total number of rows in the main array.
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rbl is a tuple with the number of left and right replica bitlines.
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Replica bit specifies which replica column this is (to determine where to put the
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replica cell relative to the bottom (including the dummy bit at 0).
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"""
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def __init__(self, name, rows, rbl, replica_bit, column_offset=0):
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# Used for pin names and properties
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self.cell = factory.create(module_type=OPTS.bitcell)
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# Row size is the number of rows with word lines
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self.row_size = sum(rbl) + rows
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# Start of regular word line rows
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self.row_start = rbl[0]
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# End of regular word line rows
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self.row_end = self.row_start + rows
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super().__init__(rows=self.row_size, cols=1, column_offset=column_offset, row_offset=0, name=name)
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self.rows = rows
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self.left_rbl = rbl[0]
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self.right_rbl = rbl[1]
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self.replica_bit = replica_bit
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# Total size includes the replica rows
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self.total_size = self.left_rbl + rows + self.right_rbl
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self.column_offset = column_offset
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debug.check(replica_bit < self.row_start or replica_bit >= self.row_end,
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"Replica bit cannot be in the regular array.")
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#if layer_props.replica_column.even_rows:
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# debug.check(rows % 2 == 0 and (self.left_rbl + 1) % 2 == 0,
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# "sky130 currently requires rows to be even and to start with X mirroring"
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# + " (left_rbl must be odd) for LVS.")
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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self.add_modules()
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self.add_pins()
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self.create_instances()
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def create_layout(self):
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self.place_array()
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self.add_layout_pins()
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self.route_supplies()
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self.add_boundary()
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self.DRC_LVS()
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def add_pins(self):
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self.create_all_bitline_names()
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self.create_all_wordline_names(self.row_size)
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self.add_pin_list(self.all_bitline_names, "OUTPUT")
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self.add_pin_list(self.all_wordline_names, "INPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def add_modules(self):
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self.replica_cell = factory.create(module_type=OPTS.replica_bitcell)
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self.dummy_cell = factory.create(module_type=OPTS.dummy_bitcell)
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def create_instances(self):
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self.cell_inst = {}
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core_block = [[0 for x in range(1)] for y in range(self.total_size)]
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current_row = self.row_start
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for row in range(self.total_size):
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# Regular array cells are replica cells
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# Replic bit specifies which other bit (in the full range (0,total_size) to make a replica cell.
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# All other cells are dummies
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if (row == self.replica_bit) or (row >= self.row_start and row < self.row_end):
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if current_row % 2 == 0:
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core_block[row][0] = geometry.instance("rbc_{}".format(row), mod=self.replica_cell, is_bitcell=True)
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else:
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core_block[row][0] = geometry.instance("rbc_{}".format(row), mod=self.replica_cell, is_bitcell=True, mirror='MX')
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else:
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if current_row % 2 == 0:
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core_block[row][0] = geometry.instance("rbc_{}".format(row), mod=self.dummy_cell, is_bitcell=True)
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else:
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core_block[row][0] = geometry.instance("rbc_{}".format(row), mod=self.dummy_cell, is_bitcell=True, mirror='MX')
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current_row += 1
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if self.cell.mirror.y:
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for row in range(self.total_size):
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if self.column_offset % 2 == 0:
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if core_block[row][0].mirror=='MX':
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core_block[row][0].mirror='XY'
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else:
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core_block[row][0].mirror='MY'
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self.pattern = pattern(self, "bitcell_array", core_block, num_rows=self.total_size, num_cols=self.column_size, name_template="rbc_r{0}_c{1}")
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self.pattern.connect_array()
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def get_bitcell_pins_col_cap(self, row, col):
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"""
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Creates a list of connections in the bitcell,
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indexed by column and row, for instance use in bitcell_array
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"""
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bitcell_pins = []
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for port in self.all_ports:
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bitcell_pins.extend([x for x in self.get_bitline_names(port) if x.endswith("_{0}".format(col))])
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if len(self.edge_cell.get_pins("vdd")) > 0:
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bitcell_pins.append("vdd")
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if len(self.edge_cell.get_pins("gnd")) > 0:
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bitcell_pins.append("gnd")
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return bitcell_pins
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def exclude_all_but_replica(self):
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"""
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Excludes all bits except the replica cell (self.replica_bit).
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"""
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for row, cell in enumerate(self.cell_inst):
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if row != self.replica_bit:
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self.graph_inst_exclude.add(self.cell_inst[cell])
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