mirror of https://github.com/VLSIDA/OpenRAM.git
143 lines
4.6 KiB
Python
143 lines
4.6 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California
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# All rights reserved.
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#
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import debug
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import design
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from tech import drc
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import contact
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from sram_factory import factory
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from vector import vector
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from globals import OPTS
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class replica_column(design.design):
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"""
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Generate a replica bitline column for the replica array.
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"""
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def __init__(self, name, rows):
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design.design.__init__(self, name)
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# One extra row for the dummy row
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self.row_size = rows + 1
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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self.add_modules()
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self.add_pins()
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self.create_instances()
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def create_layout(self):
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self.place_instances()
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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def add_pins(self):
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column_list = self.cell.list_all_bitline_names()
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for cell_column in column_list:
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self.add_pin("{0}_{1}".format(cell_column,0))
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row_list = self.cell.list_all_wl_names()
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for row in range(self.row_size):
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for cell_row in row_list:
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self.add_pin("{0}_{1}".format(cell_row,row))
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self.add_pin("vdd")
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self.add_pin("gnd")
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def add_modules(self):
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self.replica_cell = factory.create(module_type="replica_bitcell")
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self.add_mod(self.replica_cell)
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# Used for pin names only
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self.cell = factory.create(module_type="bitcell")
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def create_instances(self):
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self.cell_inst = {}
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for row in range(self.row_size):
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name="rbc_{0}".format(row)
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self.cell_inst[row]=self.add_inst(name=name,
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mod=self.replica_cell)
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self.connect_inst(self.list_bitcell_pins(0, row))
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def create_layout(self):
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# We increase it by a well enclosure so the precharges don't overlap our wells
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self.height = self.row_size*self.cell.height
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self.width = self.cell.width
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yoffset = 0.0
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for row in range(self.row_size):
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name = "bit_r{0}_{1}".format(row,"rbl")
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# This is opposite of a bitcell array since we will be 1 row off
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if not row % 2:
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tempy = yoffset + self.cell.height
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dir_key = "MX"
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else:
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tempy = yoffset
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dir_key = ""
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self.cell_inst[row].place(offset=[0.0, tempy],
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mirror=dir_key)
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yoffset += self.cell.height
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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def add_layout_pins(self):
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""" Add the layout pins """
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row_list = self.cell.list_all_wl_names()
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column_list = self.cell.list_all_bitline_names()
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col = "rbl"
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for cell_column in column_list:
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bl_pin = self.cell_inst[0].get_pin(cell_column)
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self.add_layout_pin(text=cell_column+"_{0}".format(col),
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layer="metal2",
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offset=bl_pin.ll(),
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width=bl_pin.width(),
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height=self.height)
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for row in range(self.row_size):
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for cell_row in row_list:
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wl_pin = self.cell_inst[row].get_pin(cell_row)
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self.add_layout_pin(text=cell_row+"_{0}".format(row),
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layer="metal1",
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offset=wl_pin.ll(),
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width=self.width,
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height=wl_pin.height())
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# For every second row and column, add a via for gnd and vdd
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for row in range(self.row_size):
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inst = self.cell_inst[row]
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for pin_name in ["vdd", "gnd"]:
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self.copy_layout_pin(inst, pin_name)
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def list_bitcell_pins(self, col, row):
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""" Creates a list of connections in the bitcell,
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indexed by column and row, for instance use in bitcell_array """
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bitcell_pins = []
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pin_names = self.cell.list_all_bitline_names()
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for pin in pin_names:
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bitcell_pins.append(pin+"_{0}".format(col))
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pin_names = self.cell.list_all_wl_names()
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for pin in pin_names:
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bitcell_pins.append(pin+"_{0}".format(row))
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bitcell_pins.append("vdd")
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bitcell_pins.append("gnd")
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return bitcell_pins
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