Michael Timothy Grimes 5af56e5a3a Adding layout check for sram (1 bank) using pbitcell and 1RW port

2018-09-09 22:45:25 -07:00

..

base

Add inflate blockages and remove pins from blockages.

2018-09-05 11:06:17 -07:00

characterizer

Remove OEB signal since we split DIN/DOUT ports

2018-08-13 14:09:49 -07:00

gdsMill

Add back LEF blockages. Remove "absolute" flags from GDS output

2018-09-05 09:28:43 -07:00

modules

Generalized wl names using bitcell's list_all_wl_names function to accomodate multiport

2018-09-09 22:42:52 -07:00

pgates

Bank level layout now works with pbitcell and 1RW. Column mux and array have been altered to accomodate multiport. Multiport changes to wordline driver were removed because they were unnecessary.

2018-09-09 22:06:29 -07:00

router

Add inflate blockages and remove pins from blockages.

2018-09-05 11:06:17 -07:00

tests

Adding layout check for sram (1 bank) using pbitcell and 1RW port

2018-09-09 22:45:25 -07:00

verify

Use a .magicrc in the technology directory to read magic tech files

2018-08-30 14:20:41 -07:00

debug.py

Output debug warnings and errors to stderr. Clean up regress script a bit.

2018-07-11 09:51:28 -07:00

example_config_freepdk45.py

Clean up new code for add_modules, add_pins and netlist/layouts.

2018-08-28 10:24:09 -07:00

example_config_scn3me_subm.py

Clean up new code for add_modules, add_pins and netlist/layouts.

2018-08-28 10:24:09 -07:00

gen_stimulus.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

globals.py

Fix temp directory preservation option.

2018-09-05 10:02:12 -07:00

Makefile

Add Makefile for parallel test execution.

2018-01-22 13:39:07 -08:00

openram.py

Cleanup some items with new sram_config. Update unit tests accordingly.

2018-09-04 10:47:24 -07:00

options.py

Cleanup some items with new sram_config. Update unit tests accordingly.

2018-09-04 10:47:24 -07:00

sram_1bank.py

Commiting working version of multi-port that can generate a netlist on the sram level. Changes that will clean up the code are forthcoming.

2018-09-09 14:00:51 -07:00

sram_2bank.py

Cleanup some items with new sram_config. Update unit tests accordingly.

2018-09-04 10:47:24 -07:00

sram_4bank.py

Cleanup some items with new sram_config. Update unit tests accordingly.

2018-09-04 10:47:24 -07:00

sram_base.py

Removing din and dout list names in exchange for a read index. Write ports will always be in order (they will not skip numbers. Read ports however will skip the numbers assigned to wirte ports so the index of the read ports must be tracked.

2018-09-09 14:14:26 -07:00

sram_config.py

Cleanup some items with new sram_config. Update unit tests accordingly.

2018-09-04 10:47:24 -07:00

sram.py

Cleanup some items with new sram_config. Update unit tests accordingly.

2018-09-04 10:47:24 -07:00