mirror of https://github.com/VLSIDA/OpenRAM.git
71 lines
2.4 KiB
Python
71 lines
2.4 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from bitcell_base_array import bitcell_base_array
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from tech import drc, spice
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from globals import OPTS
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from sram_factory import factory
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import debug
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class global_bitcell_array(bitcell_base_array):
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"""
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Creates a global bitcell array with a number
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of local arrays of a sizes given by a tuple in the list.
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"""
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def __init__(self, rows, cols, ports, add_replica, name=""):
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# The total of all columns will be the number of columns
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self.cols = sum(cols)
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self.local_cols = cols
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self.rows = rows
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self.sizes = sizes
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super().__init__(rows=self.rows, cols=self.cols, name=name)
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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""" Create and connect the netlist """
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self.add_modules()
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self.add_pins()
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self.create_instances()
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def create_layout(self):
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self.place()
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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def add_modules(self):
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""" Add the modules used in this design """
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self.local_mods = []
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for i, col in enumerate(self.local_cols):
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if i==self.add_replica[0]:
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la = factory.create(module_type="local_bitcell_array", rows=row, cols=col, left_rbl=i, add_replica=True)
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elif len(self.add_replica)==2 and i==self.add_replica[2]:
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la = factory.create(module_type="local_bitcell_array", rows=row, cols=col, left_rbl=i, add_replica=True)
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else:
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la = factory.create(module_type="local_bitcell_array", rows=row, cols=col, add_replica=False)
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self.add_mod(la)
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self.local_mods.append(la)
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def create_instances(self):
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""" Create the module instances used in this design """
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self.local_inst = {}
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for i in range(self.sizes):
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name = "local_array_{0}".format(i)
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self.local_inst.append(self.add_inst(name=name,
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mod=self.local_mods[i])
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self.connect_inst(self.get_bitcell_pins(row, col))
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