mirror of https://github.com/VLSIDA/OpenRAM.git
61 lines
2.8 KiB
Python
61 lines
2.8 KiB
Python
import debug
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class verilog:
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""" Create a behavioral Verilog file for simulation."""
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def verilog_write(self,verilog_name):
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""" Write a behavioral Verilog model. """
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self.vf = open(verilog_name, "w")
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self.vf.write("// OpenRAM SRAM model\n")
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self.vf.write("// Words: {0}\n".format(self.num_words))
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self.vf.write("// Word size: {0}\n\n".format(self.word_size))
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self.vf.write("module {0}(DATA,ADDR,CSb,WEb,OEb,clk);\n".format(self.name))
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self.vf.write("\n")
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self.vf.write(" parameter DATA_WIDTH = {0} ;\n".format(self.word_size))
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self.vf.write(" parameter ADDR_WIDTH = {0} ;\n".format(self.addr_size))
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self.vf.write(" parameter RAM_DEPTH = 1 << ADDR_WIDTH;\n")
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self.vf.write(" parameter DELAY = 3 ;\n")
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self.vf.write("\n")
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self.vf.write(" inout [DATA_WIDTH-1:0] DATA;\n")
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self.vf.write(" input [ADDR_WIDTH-1:0] ADDR;\n")
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self.vf.write(" input CSb; // active low chip select\n")
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self.vf.write(" input WEb; // active low write control\n")
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self.vf.write(" input OEb; // active output enable\n")
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self.vf.write(" input clk; // clock\n")
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self.vf.write("\n")
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self.vf.write(" reg [DATA_WIDTH-1:0] data_out ;\n")
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self.vf.write(" reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];\n")
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self.vf.write("\n")
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self.vf.write(" // Tri-State Buffer control\n")
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self.vf.write(" // output : When WEb = 1, oeb = 0, csb = 0\n")
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self.vf.write(" assign DATA = (!CSb && !OEb && WEb) ? data_out : {0}'bz;\n".format(self.word_size))
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self.vf.write("\n")
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self.vf.write(" // Memory Write Block\n")
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self.vf.write(" // Write Operation : When WEb = 0, CSb = 0\n")
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self.vf.write(" always @ (posedge clk)\n")
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self.vf.write(" begin : MEM_WRITE\n")
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self.vf.write(" if ( !CSb && !WEb ) begin\n")
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self.vf.write(" mem[ADDR] = DATA;\n")
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self.vf.write(" $display($time,\" Writing %m ABUS=%b DATA=%b\",ADDR,DATA);\n")
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self.vf.write(" end\n")
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self.vf.write(" end\n\n")
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self.vf.write("\n")
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self.vf.write(" // Memory Read Block\n")
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self.vf.write(" // Read Operation : When WEb = 1, CSb = 0\n")
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self.vf.write(" always @ (posedge clk)\n")
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self.vf.write(" begin : MEM_READ\n")
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self.vf.write(" if (!CSb && WEb) begin\n")
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self.vf.write(" data_out <= #(DELAY) mem[ADDR];\n")
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self.vf.write(" $display($time,\" Reading %m ABUS=%b DATA=%b\",ADDR,mem[ADDR]);\n")
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self.vf.write(" end\n")
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self.vf.write(" end\n")
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self.vf.write("\n")
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self.vf.write("endmodule\n")
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self.vf.close()
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