mirror of https://github.com/VLSIDA/OpenRAM.git
130 lines
4.0 KiB
Python
Executable File
130 lines
4.0 KiB
Python
Executable File
#!/usr/bin/env python2.7
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"""
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SRAM Compiler
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The output files append the given suffixes to the output name:
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a spice (.sp) file for circuit simulation
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a GDS2 (.gds) file containing the layout
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a LEF (.lef) file for preliminary P&R (real one should be from layout)
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a Liberty (.lib) file for timing analysis/optimization
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"""
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import sys,os
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import datetime
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import re
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import importlib
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import globals
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(OPTS, args) = globals.parse_args()
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def print_time(name, now_time, last_time=None):
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if last_time:
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time = round((now_time-last_time).total_seconds(),1)
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else:
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time = now_time
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print("** {0}: {1} seconds".format(name,time))
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return now_time
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# These depend on arguments, so don't load them until now.
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import debug
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# required positional args for using openram main exe
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if len(args) < 1:
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print(globals.USAGE)
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sys.exit(2)
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globals.print_banner()
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globals.init_openram(args[0])
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# Check if all arguments are integers for bits, size, banks
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if type(OPTS.word_size)!=int:
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debug.error("{0} is not an integer in config file.".format(OPTS.word_size))
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if type(OPTS.num_words)!=int:
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debug.error("{0} is not an integer in config file.".format(OPTS.sram_size))
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if type(OPTS.num_banks)!=int:
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debug.error("{0} is not an integer in config file.".format(OPTS.num_banks))
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if not OPTS.tech_name:
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debug.error("Tech name must be specified in config file.")
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word_size = OPTS.word_size
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num_words = OPTS.num_words
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num_banks = OPTS.num_banks
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if (OPTS.output_name == ""):
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OPTS.output_name = "sram_{0}_{1}_{2}_{3}".format(word_size,
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num_words,
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num_banks,
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OPTS.tech_name)
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print("Output files are " + OPTS.output_name + ".(sp|gds|v|lib|lef)")
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print("Technology: {0}".format(OPTS.tech_name))
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print("Word size: {0}\nWords: {1}\nBanks: {2}".format(word_size,num_words,num_banks))
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# only start importing modules after we have the config file
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import verify
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import sram
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start_time = datetime.datetime.now()
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last_time = start_time
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print_time("Start",datetime.datetime.now())
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if not OPTS.check_lvsdrc:
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print("DRC/LVS/PEX checking is disabled.")
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# import SRAM test generation
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s = sram.sram(word_size=word_size,
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num_words=num_words,
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num_banks=num_banks,
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name=OPTS.output_name)
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last_time=print_time("SRAM creation", datetime.datetime.now(), last_time)
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# Output the files for the resulting SRAM
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spname = OPTS.output_path + s.name + ".sp"
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print("SP: Writing to {0}".format(spname))
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s.sp_write(spname)
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last_time=print_time("Spice writing", datetime.datetime.now(), last_time)
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# Output the extracted design
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sram_file = spname
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if OPTS.use_pex:
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sram_file = OPTS.output_path + "temp_pex.sp"
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verify.run_pex(s.name, gdsname, spname, output=sram_file)
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# Characterize the design
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from characterizer import lib
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libname = OPTS.output_path + s.name + ".lib"
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print("LIB: Writing to {0}".format(libname))
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if OPTS.analytical_delay:
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print("Using analytical delay models (no characterization)")
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else:
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if OPTS.spice_name!="":
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print("Performing simulation-based characterization with {}".format(OPTS.spice_name))
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if OPTS.trim_netlist:
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print("Trimming netlist to speed up characterization.")
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lib.lib(libname,s,sram_file)
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last_time=print_time("Characterization", datetime.datetime.now(), last_time)
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# Write the layout
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gdsname = OPTS.output_path + s.name + ".gds"
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print("GDS: Writing to {0}".format(gdsname))
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s.gds_write(gdsname)
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last_time=print_time("GDS", datetime.datetime.now(), last_time)
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# Create a LEF physical model
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lefname = OPTS.output_path + s.name + ".lef"
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print("LEF: Writing to {0}".format(lefname))
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s.lef_write(lefname)
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last_time=print_time("LEF", datetime.datetime.now(), last_time)
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# Write a verilog model
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vname = OPTS.output_path + s.name + ".v"
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print("Verilog: Writing to {0}".format(vname))
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s.verilog_write(vname)
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last_time=print_time("Verilog", datetime.datetime.now(), last_time)
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globals.end_openram()
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print_time("End",datetime.datetime.now(), start_time)
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