mirror of https://github.com/VLSIDA/OpenRAM.git
541 lines
25 KiB
Python
541 lines
25 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2024 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import math
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import random
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import time
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import collections
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from os import path
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import shutil
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from numpy import binary_repr
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from openram import debug
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from openram import OPTS
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from .stimuli import *
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from .charutils import *
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from .simulation import simulation
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from .measurements import voltage_at_measure
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class functional(simulation):
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"""
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Functions to write random data values to a random address then read them back and check
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for successful SRAM operation.
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"""
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def __init__(self, sram, spfile=None, corner=None, cycles=15, period=None, output_path=None):
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super().__init__(sram, spfile, corner)
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# Seed the characterizer with a constant seed for unit tests
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if OPTS.is_unit_test:
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random.seed(12345)
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elif OPTS.functional_seed:
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random.seed(OPTS.functional_seed)
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else:
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seed = time.time_ns()
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random.seed(seed)
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debug.info(1, "Random seed for functional simulation: {}".format(seed))
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if not spfile:
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# self.sp_file is assigned in base class
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sram.sp_write(self.sp_file, trim=OPTS.trim_netlist)
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# Copy sp file to temp dir
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self.temp_spice = path.join(OPTS.openram_temp, "sram.sp")
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try:
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shutil.copy(self.sp_file, self.temp_spice)
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except shutil.SameFileError: # skip if the same
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pass
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if not corner:
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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if not output_path:
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self.output_path = OPTS.openram_temp
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else:
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self.output_path = output_path
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if self.write_size != self.word_size:
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self.num_wmasks = int(math.ceil(self.word_size / self.write_size))
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else:
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self.num_wmasks = 0
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if not self.num_spare_cols:
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self.num_spare_cols = 0
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self.max_data = 2 ** self.word_size - 1
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self.max_col_data = 2 ** self.num_spare_cols - 1
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if self.words_per_row > 1:
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# This will truncate bits for word addressing in a row_addr_dff
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# This makes one set of spares per row by using top bits of the address
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self.addr_spare_index = -int(math.log(self.words_per_row) / math.log(2))
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else:
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# This will select the entire address when one word per row
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self.addr_spare_index = self.bank_addr_size
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# If trim is set, specify the valid addresses
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self.valid_addresses = set()
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self.max_address = self.num_rows * self.words_per_row - 1
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if OPTS.trim_netlist:
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for i in range(self.words_per_row):
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self.valid_addresses.add(i)
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self.valid_addresses.add(self.max_address - i - 1)
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self.probe_address, self.probe_data = '0' * self.bank_addr_size, 0
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self.set_corner(corner)
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self.set_spice_constants()
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self.set_stimulus_variables()
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# Override default period
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if period:
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self.period = period
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# For the debug signal names
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self.wordline_row = 0
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self.bitline_column = 0
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self.create_signal_names()
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#self.add_graph_exclusions()
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#self.create_graph()
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#self.set_internal_spice_names()
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self.bl_name = "xsram:xbank0:bl_0_{}"
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self.br_name = "xsram:xbank0:br_0_{}"
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self.sen_name = "xsram:s_en"
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self.q_name, self.qbar_name = self.get_bit_name()
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debug.info(2, "q:\t\t{0}".format(self.q_name))
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debug.info(2, "qbar:\t{0}".format(self.qbar_name))
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debug.info(2, "s_en:\t{0}".format(self.sen_name))
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debug.info(2, "bl:\t{0}".format(self.bl_name))
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debug.info(2, "br:\t{0}".format(self.br_name))
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# Number of checks can be changed
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self.num_cycles = cycles
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# This is to have ordered keys for random selection
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self.stored_words = collections.OrderedDict()
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self.stored_spares = collections.OrderedDict()
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self.read_check = []
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self.read_results = []
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# Generate a random sequence of reads and writes
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self.create_random_memory_sequence()
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# Write SPICE simulation
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self.write_functional_stimulus()
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def run(self):
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self.stim.run_sim(self.stim_sp)
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# read dout values from SPICE simulation. If the values do not fall within the noise margins, return the error.
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(success, error) = self.read_stim_results()
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if not success:
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return (0, error)
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# Check read values with written values. If the values do not match, return an error.
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return self.check_stim_results()
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def check_lengths(self):
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""" Do a bunch of assertions. """
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for port in self.all_ports:
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checks = []
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if port in self.read_ports:
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checks.append((self.addr_value[port], "addr"))
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if port in self.write_ports:
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checks.append((self.data_value[port], "data"))
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checks.append((self.wmask_value[port], "wmask"))
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checks.append((self.spare_wen_value[port], "spare_wen"))
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for (val, name) in checks:
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debug.check(len(self.cycle_times)==len(val),
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"Port {2} lengths don't match. {0} clock values, {1} {3} values".format(len(self.cycle_times),
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len(val),
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port,
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name))
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def create_random_memory_sequence(self):
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# Select randomly, but have 3x more reads to increase probability
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if self.write_size != self.word_size:
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rw_ops = ["noop", "write", "partial_write", "read", "read"]
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w_ops = ["noop", "write", "partial_write"]
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else:
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rw_ops = ["noop", "write", "read", "read"]
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w_ops = ["noop", "write"]
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r_ops = ["noop", "read"]
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# First cycle idle is always an idle cycle
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comment = self.gen_cycle_comment("noop", "0" * self.word_size, "0" * self.bank_addr_size, "0" * self.num_wmasks, 0, self.t_current)
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self.add_noop_all_ports(comment)
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# 1. Write all the write ports 2x to seed a bunch of locations.
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for i in range(3):
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for port in self.write_ports:
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addr = self.gen_addr()
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(word, spare) = self.gen_data()
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combined_word = self.combine_word(spare, word)
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comment = self.gen_cycle_comment("write", combined_word, addr, "1" * self.num_wmasks, port, self.t_current)
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self.add_write_one_port(comment, addr, spare + word, "1" * self.num_wmasks, port)
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self.stored_words[addr] = word
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self.stored_spares[addr[:self.addr_spare_index]] = spare
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# All other read-only ports are noops.
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for port in self.read_ports:
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if port not in self.write_ports:
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self.add_noop_one_port(port)
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self.cycle_times.append(self.t_current)
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self.t_current += self.period
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self.check_lengths()
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# 2. Read at least once. For multiport, it is important that one
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# read cycle uses all RW and R port to read from the same
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# address simultaniously. This will test the viablilty of the
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# transistor sizing in the bitcell.
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for port in self.all_ports:
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if port in self.write_ports and port not in self.read_ports:
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self.add_noop_one_port(port)
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else:
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(addr, word, spare) = self.get_data()
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combined_word = self.combine_word(spare, word)
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comment = self.gen_cycle_comment("read", combined_word, addr, "0" * self.num_wmasks, port, self.t_current)
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self.add_read_one_port(comment, addr, port)
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self.add_read_check(spare + word, port)
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self.cycle_times.append(self.t_current)
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self.t_current += self.period
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self.check_lengths()
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# 3. Perform a random sequence of writes and reads on random
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# ports, using random addresses and random words and random
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# write masks (if applicable)
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for i in range(self.num_cycles):
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w_addrs = []
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for port in self.all_ports:
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if port in self.readwrite_ports:
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op = random.choice(rw_ops)
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elif port in self.write_ports:
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op = random.choice(w_ops)
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else:
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op = random.choice(r_ops)
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if op == "noop":
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self.add_noop_one_port(port)
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elif op == "write":
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addr = self.gen_addr()
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# two ports cannot write to the same address
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if addr in w_addrs:
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self.add_noop_one_port(port)
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else:
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(word, spare) = self.gen_data()
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combined_word = self.combine_word(spare, word)
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comment = self.gen_cycle_comment("write", combined_word, addr, "1" * self.num_wmasks, port, self.t_current)
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self.add_write_one_port(comment, addr, spare + word, "1" * self.num_wmasks, port)
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self.stored_words[addr] = word
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self.stored_spares[addr[:self.addr_spare_index]] = spare
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w_addrs.append(addr)
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elif op == "partial_write":
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# write only to a word that's been written to
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(addr, old_word, old_spare) = self.get_data()
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# two ports cannot write to the same address
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if addr in w_addrs:
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self.add_noop_one_port(port)
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else:
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(word, spare) = self.gen_data()
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wmask = self.gen_wmask()
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new_word = self.gen_masked_data(old_word, word, wmask)
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combined_word = self.combine_word(spare, word)
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comment = self.gen_cycle_comment("partial_write", combined_word, addr, wmask, port, self.t_current)
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self.add_write_one_port(comment, addr, spare + word, wmask, port)
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self.stored_words[addr] = new_word
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self.stored_spares[addr[:self.addr_spare_index]] = spare
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w_addrs.append(addr)
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else:
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(addr, word) = random.choice(list(self.stored_words.items()))
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spare = self.stored_spares[addr[:self.addr_spare_index]]
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combined_word = self.combine_word(spare, word)
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# The write driver is not sized sufficiently to drive through the two
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# bitcell access transistors to the read port. So, for now, we do not allow
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# a simultaneous write and read to the same address on different ports. This
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# could be even more difficult with multiple simultaneous read ports.
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if addr in w_addrs:
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self.add_noop_one_port(port)
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else:
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comment = self.gen_cycle_comment("read", combined_word, addr, "0" * self.num_wmasks, port, self.t_current)
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self.add_read_one_port(comment, addr, port)
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self.add_read_check(spare + word, port)
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self.cycle_times.append(self.t_current)
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self.t_current += self.period
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# Last cycle idle needed to correctly measure the value on the second to last clock edge
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comment = self.gen_cycle_comment("noop", "0" * self.word_size, "0" * self.bank_addr_size, "0" * self.num_wmasks, 0, self.t_current)
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self.add_noop_all_ports(comment)
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def gen_masked_data(self, old_word, word, wmask):
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""" Create the masked data word """
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# Start with the new word
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new_word = word
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# When the write mask's bits are 0, the old data values should appear in the new word
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# as to not overwrite the old values
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for bit in range(len(wmask)):
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if wmask[bit] == "0":
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lower = bit * self.write_size
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upper = lower + self.write_size - 1
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new_word = new_word[:lower] + old_word[lower:upper + 1] + new_word[upper + 1:]
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return new_word
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def add_read_check(self, word, port):
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""" Add to the check array to ensure a read works. """
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self.read_check.append([word,
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"{0}{1}".format(self.dout_name, port),
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self.t_current + self.period,
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int(self.t_current / self.period)])
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def read_stim_results(self):
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# Extract dout values from spice timing.lis
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for (word, dout_port, eo_period, cycle) in self.read_check:
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sp_read_value = ""
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for bit in range(self.word_size + self.num_spare_cols):
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measure_name = "v{0}_{1}ck{2}".format(dout_port.lower(), bit, cycle)
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# value = parse_spice_list("timing", measure_name)
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value = self.measures[measure_name].retrieve_measure(port=0)
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# FIXME: Ignore the spare columns for now
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if bit >= self.word_size:
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value = 0
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try:
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value = float(value)
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if value > self.v_high:
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sp_read_value = "1" + sp_read_value
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elif value < self.v_low:
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sp_read_value = "0" + sp_read_value
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else:
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error ="FAILED: {0}_{1} value {2} at time {3}n does not fall within noise margins <{4} or >{5}.".format(dout_port,
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bit,
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value,
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eo_period,
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self.v_low,
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self.v_high)
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except ValueError:
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error ="FAILED: {0}_{1} value {2} at time {3}n is not a float. Measure: {4}".format(dout_port,
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bit,
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value,
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eo_period,
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measure_name)
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return (0, error)
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self.read_results.append([sp_read_value, dout_port, eo_period, cycle])
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return (1, "SUCCESS")
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def check_stim_results(self):
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for i in range(len(self.read_check)):
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if self.read_check[i][0] != self.read_results[i][0]:
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output_name = self.read_check[i][1]
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cycle = self.read_check[i][3]
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read_val = self.format_value(self.read_results[i][0])
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correct_val = self.format_value(self.read_check[i][0])
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check_name = "v{0}_Xck{1}".format(output_name, cycle)
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str = "FAILED: {0} read value {1} during cycle {3} at time {4}n ({5}) does not match written value ({2})"
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error = str.format(output_name,
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read_val,
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correct_val,
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cycle,
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self.read_results[i][2],
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check_name)
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return (0, error)
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return (1, "SUCCESS")
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def gen_wmask(self):
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wmask = ""
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# generate a random wmask
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for bit in range(self.num_wmasks):
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rand = random.randint(0, 1)
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wmask += str(rand)
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# prevent the wmask from having all bits on or off (this is not a partial write)
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all_zeroes = True
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all_ones = True
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for bit in range(self.num_wmasks):
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if wmask[bit]=="0":
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all_ones = False
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elif wmask[bit]=="1":
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all_zeroes = False
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if all_zeroes:
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index = random.randint(0, self.num_wmasks - 1)
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wmask = wmask[:index] + "1" + wmask[index + 1:]
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elif all_ones:
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index = random.randint(0, self.num_wmasks - 1)
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wmask = wmask[:index] + "0" + wmask[index + 1:]
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# wmask must be reversed since a python list goes right to left and sram bits go left to right.
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return wmask[::-1]
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def gen_data(self):
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""" Generates a random word to write. """
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# Don't use 0 or max value
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random_value = random.randint(1, self.max_data)
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data_bits = binary_repr(random_value, self.word_size)
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if self.num_spare_cols>0:
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random_value = random.randint(0, self.max_col_data)
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spare_bits = binary_repr(random_value, self.num_spare_cols)
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else:
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spare_bits = ""
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# FIXME: Set these to 0 for now...
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spare_bits = "0" * len(spare_bits)
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return data_bits, spare_bits
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def gen_addr(self):
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""" Generates a random address value to write to. """
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if self.valid_addresses:
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random_value = random.sample(list(self.valid_addresses), 1)[0]
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else:
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random_value = random.randint(0, self.max_address)
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addr_bits = binary_repr(random_value, self.bank_addr_size)
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return addr_bits
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def get_data(self):
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""" Gets an available address and corresponding word. """
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# Used for write masks since they should be writing to previously written addresses
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addr = random.choice(list(self.stored_words.keys()))
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word = self.stored_words[addr]
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spare = self.stored_spares[addr[:self.addr_spare_index]]
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return (addr, word, spare)
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def write_functional_stimulus(self):
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""" Writes SPICE stimulus. """
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self.stim_sp = "functional_stim.sp"
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temp_stim = path.join(self.output_path, self.stim_sp)
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self.sf = open(temp_stim, "w")
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self.sf.write("* Functional test stimulus file for {0}ns period\n\n".format(self.period))
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self.meas_sp = "functional_meas.sp"
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temp_meas = path.join(self.output_path, self.meas_sp)
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self.mf = open(temp_meas, "w")
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self.stim = stimuli(self.sf, self.mf, self.corner)
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# Write include statements
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self.stim.write_include(self.temp_spice)
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# Write Vdd/Gnd statements
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self.sf.write("\n* Global Power Supplies\n")
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self.stim.write_supply()
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# Instantiate the SRAM
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self.sf.write("\n* Instantiation of the SRAM\n")
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self.stim.inst_model(pins=self.pins,
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model_name=self.sram.name)
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# Add load capacitance to each of the read ports
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self.sf.write("\n* SRAM output loads\n")
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for port in self.read_ports:
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for bit in range(self.word_size + self.num_spare_cols):
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sig_name="{0}{1}_{2} ".format(self.dout_name, port, bit)
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self.sf.write("CD{0}{1} {2} 0 {3}f\n".format(port, bit, sig_name, self.load))
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# Write important signals to stim file
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self.sf.write("\n\n* Important signals for debug\n")
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self.sf.write("* bl:\t{0}\n".format(self.bl_name.format(port)))
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self.sf.write("* br:\t{0}\n".format(self.br_name.format(port)))
|
|
self.sf.write("* s_en:\t{0}\n".format(self.sen_name))
|
|
self.sf.write("* q:\t{0}\n".format(self.q_name))
|
|
self.sf.write("* qbar:\t{0}\n".format(self.qbar_name))
|
|
|
|
# Write debug comments to stim file
|
|
self.sf.write("\n\n* Sequence of operations\n")
|
|
for comment in self.fn_cycle_comments:
|
|
self.sf.write("*{0}\n".format(comment))
|
|
|
|
# Generate data input bits
|
|
self.sf.write("\n* Generation of data and address signals\n")
|
|
for port in self.write_ports:
|
|
for bit in range(self.word_size + self.num_spare_cols):
|
|
sig_name="{0}{1}_{2} ".format(self.din_name, port, bit)
|
|
self.stim.gen_pwl(sig_name, self.cycle_times, self.data_values[port][bit], self.period, self.slew, 0.05)
|
|
|
|
# Generate address bits
|
|
for port in self.all_ports:
|
|
for bit in range(self.bank_addr_size):
|
|
sig_name="{0}{1}_{2} ".format(self.addr_name, port, bit)
|
|
self.stim.gen_pwl(sig_name, self.cycle_times, self.addr_values[port][bit], self.period, self.slew, 0.05)
|
|
|
|
# Generate control signals
|
|
self.sf.write("\n * Generation of control signals\n")
|
|
for port in self.all_ports:
|
|
self.stim.gen_pwl("CSB{0}".format(port), self.cycle_times, self.csb_values[port], self.period, self.slew, 0.05)
|
|
|
|
for port in self.readwrite_ports:
|
|
self.stim.gen_pwl("WEB{0}".format(port), self.cycle_times, self.web_values[port], self.period, self.slew, 0.05)
|
|
|
|
# Generate wmask bits
|
|
for port in self.write_ports:
|
|
if self.write_size != self.word_size:
|
|
self.sf.write("\n* Generation of wmask signals\n")
|
|
for bit in range(self.num_wmasks):
|
|
sig_name = "WMASK{0}_{1} ".format(port, bit)
|
|
# self.stim.gen_pwl(sig_name, self.cycle_times, self.data_values[port][bit], self.period,
|
|
# self.slew, 0.05)
|
|
self.stim.gen_pwl(sig_name, self.cycle_times, self.wmask_values[port][bit], self.period,
|
|
self.slew, 0.05)
|
|
|
|
# Generate spare enable bits (for spare cols)
|
|
for port in self.write_ports:
|
|
if self.num_spare_cols:
|
|
self.sf.write("\n* Generation of spare enable signals\n")
|
|
for bit in range(self.num_spare_cols):
|
|
sig_name = "SPARE_WEN{0}_{1} ".format(port, bit)
|
|
self.stim.gen_pwl(sig_name, self.cycle_times, self.spare_wen_values[port][bit], self.period,
|
|
self.slew, 0.05)
|
|
|
|
# Generate CLK signals
|
|
for port in self.all_ports:
|
|
self.stim.gen_pulse(sig_name="{0}{1}".format("clk", port),
|
|
v1=self.gnd_voltage,
|
|
v2=self.vdd_voltage,
|
|
offset=self.period - 0.5 * self.slew,
|
|
period=self.period,
|
|
t_rise=self.slew,
|
|
t_fall=self.slew)
|
|
|
|
# Generate dout value measurements
|
|
self.sf.write("\n * Generation of dout measurements\n")
|
|
self.measures = {}
|
|
|
|
for (word, dout_port, eo_period, cycle) in self.read_check:
|
|
t_initial = eo_period
|
|
t_final = eo_period + 0.01 * self.period
|
|
num_bits = self.word_size + self.num_spare_cols
|
|
for bit in range(num_bits):
|
|
signal_name = "{0}_{1}".format(dout_port, bit)
|
|
measure_name = "v{0}ck{1}".format(signal_name, cycle)
|
|
voltage_value = self.stim.get_voltage(word[num_bits - bit - 1])
|
|
|
|
self.stim.add_comment("* CHECK {0} {1} = {2} time = {3}".format(signal_name,
|
|
measure_name,
|
|
voltage_value,
|
|
eo_period))
|
|
# TODO: Convert to measurement statement instead of stimuli
|
|
meas = voltage_at_measure(measure_name, signal_name)
|
|
self.measures[measure_name] = meas
|
|
meas.write_measure(self.stim, ((t_initial + t_final) / 2, 0))
|
|
# self.stim.gen_meas_value(meas_name=measure_name,
|
|
# dout=signal_name,
|
|
# t_initial=t_initial,
|
|
# t_final=t_final
|
|
|
|
self.sf.write(".include {0}\n".format(temp_meas))
|
|
self.stim.write_control(self.cycle_times[-1] + self.period)
|
|
self.sf.close()
|
|
self.mf.close()
|
|
|
|
# FIXME: Similar function to delay.py, refactor this
|
|
def get_bit_name(self):
|
|
""" Get a bit cell name """
|
|
# TODO: Find a way to get the cell_name and storage_names statically
|
|
# (cell_name, cell_inst) = self.sram.get_cell_name(self.sram.name, 0, 0)
|
|
# storage_names = cell_inst.mod.get_storage_net_names()
|
|
# debug.check(len(storage_names) == 2, ("Only inverting/non-inverting storage nodes"
|
|
# "supported for characterization. Storage nets={0}").format(storage_names))
|
|
cell_name = "xsram:xbank0:xbitcell_array:xbitcell_array:xbit_r0_c0"
|
|
storage_names = ("Q", "Q_bar")
|
|
q_name = cell_name + OPTS.hier_seperator + str(storage_names[0])
|
|
qbar_name = cell_name + OPTS.hier_seperator + str(storage_names[1])
|
|
|
|
return (q_name, qbar_name)
|