Matt Guthaus 550d5cc729 Fix path to config file in test 30

2018-11-09 16:33:08 -08:00

..

base

Merge branch 'dev' into datasheet_gen

2018-11-08 19:26:00 -08:00

bitcells

Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport

2018-11-08 09:59:52 -08:00

characterizer

added area to datasheet

2018-11-08 21:30:17 -08:00

datasheet

added area to datasheet

2018-11-08 21:30:17 -08:00

drc

Moving wide metal spacing to routing grid level

2018-10-15 09:59:16 -07:00

gdsMill

Allow multiple must-connect pins with the same label.

2018-11-07 13:05:13 -08:00

modules

Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.

2018-11-07 11:31:44 -08:00

pgates

Altering the routing slightly in the column mux to give the gnd contacts a wider berth. This prevents drc errors when the bitlines are close to the edge of the cell.

2018-11-02 05:59:47 -07:00

router

Allow multiple must-connect pins with the same label.

2018-11-07 13:05:13 -08:00

tests

Fix path to config file in test 30

2018-11-09 16:33:08 -08:00

verify

Remove redundant DRC run in magic.

2018-11-05 13:30:42 -08:00

debug.py

Output debug warnings and errors to stderr. Clean up regress script a bit.

2018-07-11 09:51:28 -07:00

example_config_freepdk45.py

Remove options from example config files

2018-11-05 12:47:47 -08:00

example_config_scn4m_subm.py

Add magic/netgen to example config

2018-11-07 13:54:00 -08:00

gen_stimulus.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

globals.py

added config file to datasheet and output files

2018-10-31 12:29:13 -07:00

Makefile

Add Makefile for parallel test execution.

2018-01-22 13:39:07 -08:00

openram.py

added config file to datasheet and output files

2018-10-31 12:29:13 -07:00

options.py

Fix openram_temp directory

2018-10-06 08:08:01 -07:00

sram_1bank.py

Merge branch 'multiport' into supply_routing

2018-10-11 09:56:38 -07:00

sram_2bank.py

Cleanup some items with new sram_config. Update unit tests accordingly.

2018-09-04 10:47:24 -07:00

sram_4bank.py

Converted all submodules to use _bit notation instead of [bit]

2018-10-11 09:53:08 -07:00

sram_base.py

Altered bitline with heuristic to have a larger delay chain for larger column muxes. Also have to alter the feasible period for functional tests to pass.

2018-10-30 22:19:26 -07:00

sram_config.py

Added custom 1rw+1r bitcell. Testing are currently failing.

2018-10-22 17:02:21 -07:00

sram.py

added area to datasheet

2018-11-08 21:30:17 -08:00