mirror of https://github.com/VLSIDA/OpenRAM.git
249 lines
9.0 KiB
Python
249 lines
9.0 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California
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# All rights reserved.
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#
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from math import log, ceil
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import debug
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import design
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from sram_factory import factory
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from vector import vector
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from tech import layer, drc
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from globals import OPTS
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from tech import layer_properties as layer_props
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class port_address(design.design):
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"""
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Create the address port (row decoder and wordline driver)..
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"""
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def __init__(self, cols, rows, port, name=""):
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self.num_cols = cols
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self.num_rows = rows
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self.port = port
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self.addr_size = ceil(log(self.num_rows, 2))
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if name == "":
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name = "port_address_{0}_{1}".format(cols, rows)
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super().__init__(name)
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debug.info(2, "create data port of cols {0} rows {1}".format(cols, rows))
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self.create_netlist()
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if not OPTS.netlist_only:
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debug.check(len(self.all_ports) <= 2, "Bank layout cannot handle more than two ports.")
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self.create_layout()
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self.add_boundary()
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def create_netlist(self):
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self.add_pins()
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self.add_modules()
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self.create_row_decoder()
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self.create_wordline_driver()
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self.create_rbl_driver()
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def create_layout(self):
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if "li" in layer:
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self.route_layer = "li"
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else:
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self.route_layer = "m1"
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self.place_instances()
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self.route_layout()
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self.DRC_LVS()
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def add_pins(self):
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""" Adding pins for port address module"""
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for bit in range(self.addr_size):
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self.add_pin("addr_{0}".format(bit), "INPUT")
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self.add_pin("wl_en", "INPUT")
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for bit in range(self.num_rows):
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self.add_pin("wl_{0}".format(bit), "OUTPUT")
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self.add_pin("rbl_wl", "OUTPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def route_layout(self):
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""" Create routing amoung the modules """
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self.route_pins()
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self.route_internal()
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self.route_supplies()
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def route_supplies(self):
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""" Propagate all vdd/gnd pins up to this level for all modules """
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for inst in [self.wordline_driver_array_inst, self.row_decoder_inst]:
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self.copy_power_pins(inst, "vdd")
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self.copy_power_pins(inst, "gnd")
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for rbl_vdd_pin in self.rbl_driver_inst.get_pins("vdd"):
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if layer_props.port_address.supply_offset:
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self.copy_power_pin(rbl_vdd_pin)
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else:
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self.copy_power_pin(rbl_vdd_pin, loc=rbl_vdd_pin.lc())
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# Also connect the B input of the RBL and_dec to vdd
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if OPTS.local_array_size == 0:
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rbl_b_pin = self.rbl_driver_inst.get_pin("B")
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rbl_loc = rbl_b_pin.center() - vector(3 * self.m1_pitch, 0)
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self.add_path(rbl_b_pin.layer, [rbl_b_pin.center(), rbl_loc])
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self.add_power_pin("vdd", rbl_loc, start_layer=rbl_b_pin.layer)
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def route_pins(self):
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for row in range(self.addr_size):
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decoder_name = "addr_{}".format(row)
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self.copy_layout_pin(self.row_decoder_inst, decoder_name)
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for row in range(self.num_rows):
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driver_name = "wl_{}".format(row)
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self.copy_layout_pin(self.wordline_driver_array_inst, driver_name)
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self.copy_layout_pin(self.rbl_driver_inst, "Z", "rbl_wl")
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def route_internal(self):
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for row in range(self.num_rows):
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# The pre/post is to access the pin from "outside" the cell to avoid DRCs
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decoder_out_pin = self.row_decoder_inst.get_pin("decode_{}".format(row))
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decoder_out_pos = decoder_out_pin.rc()
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driver_in_pin = self.wordline_driver_array_inst.get_pin("in_{}".format(row))
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driver_in_pos = driver_in_pin.lc()
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self.add_zjog(self.route_layer, decoder_out_pos, driver_in_pos, var_offset=0.3)
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self.add_via_stack_center(from_layer=decoder_out_pin.layer,
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to_layer=self.route_layer,
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offset=decoder_out_pos)
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self.add_via_stack_center(from_layer=driver_in_pin.layer,
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to_layer=self.route_layer,
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offset=driver_in_pos)
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# Route the RBL from the enable input
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en_pin = self.wordline_driver_array_inst.get_pin("en")
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if self.port == 0:
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en_pos = en_pin.bc()
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else:
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en_pos = en_pin.uc()
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rbl_in_pin = self.rbl_driver_inst.get_pin("A")
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rbl_in_pos = rbl_in_pin.center()
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self.add_via_stack_center(from_layer=rbl_in_pin.layer,
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to_layer=en_pin.layer,
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offset=rbl_in_pos)
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self.add_zjog(layer=en_pin.layer,
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start=rbl_in_pos,
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end=en_pos,
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first_direction="V")
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self.add_layout_pin_rect_center(text="wl_en",
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layer=en_pin.layer,
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offset=rbl_in_pos)
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def add_modules(self):
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self.row_decoder = factory.create(module_type="decoder",
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num_outputs=self.num_rows)
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self.wordline_driver_array = factory.create(module_type="wordline_driver_array",
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rows=self.num_rows,
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cols=self.num_cols)
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local_array_size = OPTS.local_array_size
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if local_array_size > 0:
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driver_size = max(int(self.num_cols / local_array_size), 1)
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else:
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# Defautl to FO4
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driver_size = max(int(self.num_cols / 4), 1)
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# The polarity must be switched if we have a hierarchical wordline
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# to compensate for the local array inverters
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b = factory.create(module_type=OPTS.bitcell)
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if local_array_size > 0:
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# The local wordline driver will change the polarity
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self.rbl_driver = factory.create(module_type="inv_dec",
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size=driver_size,
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height=b.height)
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else:
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# There is no local wordline driver
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self.rbl_driver = factory.create(module_type="and2_dec",
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size=driver_size,
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height=b.height)
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def create_row_decoder(self):
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""" Create the hierarchical row decoder """
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self.row_decoder_inst = self.add_inst(name="row_decoder",
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mod=self.row_decoder)
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temp = []
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for bit in range(self.addr_size):
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temp.append("addr_{0}".format(bit))
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for row in range(self.num_rows):
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temp.append("dec_out_{0}".format(row))
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temp.extend(["vdd", "gnd"])
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self.connect_inst(temp)
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def create_rbl_driver(self):
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""" Create the RBL Wordline Driver """
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self.rbl_driver_inst = self.add_inst(name="rbl_driver",
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mod=self.rbl_driver)
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temp = []
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temp.append("wl_en")
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if OPTS.local_array_size == 0:
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temp.append("vdd")
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temp.append("rbl_wl")
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temp.append("vdd")
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temp.append("gnd")
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self.connect_inst(temp)
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def create_wordline_driver(self):
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""" Create the Wordline Driver """
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self.wordline_driver_array_inst = self.add_inst(name="wordline_driver",
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mod=self.wordline_driver_array)
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temp = []
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for row in range(self.num_rows):
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temp.append("dec_out_{0}".format(row))
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for row in range(self.num_rows):
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temp.append("wl_{0}".format(row))
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temp.append("wl_en")
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temp.append("vdd")
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temp.append("gnd")
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self.connect_inst(temp)
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def place_instances(self):
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"""
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Compute the offsets and place the instances.
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"""
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row_decoder_offset = vector(0, 0)
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self.row_decoder_inst.place(row_decoder_offset)
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wordline_driver_array_offset = vector(self.row_decoder_inst.rx(), 0)
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self.wordline_driver_array_inst.place(wordline_driver_array_offset)
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# The wordline driver also had an extra gap on the right, so use this offset
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well_gap = 2 * drc("pwell_to_nwell") + drc("nwell_enclose_active")
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x_offset = self.wordline_driver_array_inst.rx() - well_gap - self.rbl_driver.width
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if self.port == 0:
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rbl_driver_offset = vector(x_offset,
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0)
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self.rbl_driver_inst.place(rbl_driver_offset, "MX")
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else:
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rbl_driver_offset = vector(x_offset,
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self.wordline_driver_array.height)
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self.rbl_driver_inst.place(rbl_driver_offset)
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# Pass this up
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self.predecoder_height = self.row_decoder.predecoder_height
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self.height = self.row_decoder.height
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self.width = self.wordline_driver_array_inst.rx()
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