mirror of https://github.com/VLSIDA/OpenRAM.git
70 lines
3.3 KiB
Python
70 lines
3.3 KiB
Python
#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2023 Regents of the University of California
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# All rights reserved.
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#
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from openram.base import geometry
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from openram.sram_factory import factory
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from openram.tech import layer
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from openram import OPTS
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from .sky130_bitcell_base_array import sky130_bitcell_base_array
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from openram.modules import dummy_array
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from openram.modules import pattern
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from math import ceil
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class sky130_dummy_array(dummy_array, sky130_bitcell_base_array):
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"""
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Generate a dummy row/column for the replica array.
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"""
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def __init__(self, rows, cols, column_offset=0, row_offset=0 ,mirror=0, location="", name=""):
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super().__init__(rows=rows, cols=cols, column_offset=column_offset, name=name)
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def add_modules(self):
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""" Add the modules used in this design """
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self.dummy_cell = factory.create(module_type=OPTS.dummy_bitcell, version="opt1")
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self.dummy_cella = factory.create(module_type=OPTS.dummy_bitcell, version="opt1a")
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self.strap = factory.create(module_type="internal", version="wlstrap")
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self.strap_p = factory.create(module_type="internal", version="wlstrap_p")
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self.strapa = factory.create(module_type="internal", version="wlstrapa")
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self.strapa_p = factory.create(module_type="internal", version="wlstrapa_p")
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self.cell = factory.create(module_type=OPTS.bitcell, version="opt1")
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def create_instances(self):
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""" Create the module instances used in this design """
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# this code needs to use connect_array_raw() to make dummy columns correctly, but single port shouldn't need these since there are dedicated cap cells
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self.all_inst={}
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self.cell_inst={}
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bit_row_opt1 = [geometry.instance("00_opt1", mod=self.dummy_cell, is_bitcell=True, mirror='MY')] \
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+ [geometry.instance("01_strap_p", mod=self.strap_p, is_bitcell=False, mirror='')]\
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+ [geometry.instance("02_opt1", mod=self.dummy_cell, is_bitcell=True, mirror='')] \
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+ [geometry.instance("03_strap", mod=self.strap, is_bitcell=False, mirror='')]
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bit_row_opt1a = [geometry.instance("10_opt1a", mod=self.dummy_cella, is_bitcell=True, mirror='MY')] \
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+ [geometry.instance("11_strap_p", mod=self.strap_p, is_bitcell=False)] \
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+ [geometry.instance("12_opt1a", mod=self.dummy_cella, is_bitcell=True)] \
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+ [geometry.instance("13_strapaa", mod=self.strapa, is_bitcell=False)]
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bit_block = []
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if(self.row_offset % 2 == 0):
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next_row = 1
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else:
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next_row = 0
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for i in range(self.row_size):
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if next_row == 0:
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pattern.append_row_to_block(bit_block, bit_row_opt1)
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next_row = 1
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else:
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pattern.append_row_to_block(bit_block, bit_row_opt1a)
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next_row = 0
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for row in bit_block:
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row = pattern.rotate_list(row, self.column_offset * 2)
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self.pattern = pattern(self, "bitcell_array", bit_block, num_rows=self.row_size, num_cols=self.column_size, num_cores_x=ceil(self.column_size/2), num_cores_y=ceil(self.row_size/2), name_template="dummy_bit_r{0}_c{1}")
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self.pattern.connect_array()
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