mirror of https://github.com/VLSIDA/OpenRAM.git
120 lines
4.4 KiB
Python
120 lines
4.4 KiB
Python
#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2023 Regents of the University of California
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# All rights reserved.
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#
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from openram import debug
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from openram.base import geometry
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from openram.modules import bitcell_base_array
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from openram.sram_factory import factory
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from openram.tech import layer
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from openram import OPTS
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from openram.modules import pattern
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class sky130_bitcell_base_array(bitcell_base_array):
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"""
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Abstract base class for bitcell-arrays -- bitcell, dummy, replica
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"""
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def __init__(self, name, rows, cols, column_offset):
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super().__init__(name, rows, cols, column_offset)
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debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols))
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self.cell = factory.create(module_type=OPTS.bitcell, version="opt1")
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def get_bitcell_pins(self, row, col, swap = False):
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"""
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Creates a list of connections in the bitcell,
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indexed by column and row, for instance use in bitcell_array
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"""
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bitcell_pins = []
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for port in self.all_ports:
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bitcell_pins.extend([x for x in self.get_bitline_names(port) if x.endswith("_{0}".format(col))])
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bitcell_pins.append("gnd") # gnd
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bitcell_pins.append("vdd") # vdd
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bitcell_pins.append("vdd") # vpb
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bitcell_pins.append("gnd") # vnb
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bitcell_pins.extend([x for x in self.all_wordline_names if x.endswith("_{0}".format(row))])
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return bitcell_pins
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def get_strap_pins(self, row, col, name=""):
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"""
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Creates a list of connections in the strap cell,
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indexed by column and row, for instance use in bitcell_array
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"""
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if name and "_p" in name:
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strap_pins = ["gnd"]
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else:
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strap_pins = ["vdd"]
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return strap_pins
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def get_col_cap_p_pins(self, row, col):
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"""
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"""
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strap_pins = ["gnd", "vdd", "gnd"]
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return strap_pins
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def get_col_cap_pins(self, row, col):
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"""
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"""
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strap_pins = []
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for port in self.all_ports:
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strap_pins.extend([x for x in self.get_bitline_names(port) if "bl" in x and x.endswith("_{0}".format(col))])
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strap_pins.extend(["vdd", "gnd"])
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for port in self.all_ports:
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strap_pins.extend([x for x in self.get_bitline_names(port) if "br" in x and x.endswith("_{0}".format(col))])
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if row == 0:
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strap_pins.extend(["top_gate"])
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else:
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strap_pins.extend(["bot_gate"])
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strap_pins.extend(["vdd", "gnd"])
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return strap_pins
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def get_row_cap_pins(self, row, col):
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"""
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"""
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strap_pins = ["gnd", "vdd", "gnd"]
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return strap_pins
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def get_corner_pins(self):
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"""
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"""
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strap_pins = ["vdd", "gnd", "vdd"]
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return strap_pins
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def route_supplies(self):
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# Copy a vdd/gnd layout pin from every cell
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super().route_supplies()
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for inst in self.insts:
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if "VPWR" in inst.mod.pins:
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self.copy_layout_pin(inst, "VPWR", "vdd")
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if "VGND" in inst.mod.pins:
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self.copy_layout_pin(inst, "VGND", "gnd")
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if hasattr(self, 'cell_inst'):
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for col in range(self.column_size):
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inst = self.cell_inst[0,col]
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pin = inst.get_pin("vpb")
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self.objs.append(geometry.rectangle(layer["nwell"],
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pin.ll(),
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pin.width(),
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pin.height()))
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self.objs.append(geometry.label("vdd", layer["nwell"], pin.center()))
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try:
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from openram.tech import layer_override
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if layer_override['VNB']:
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pin = inst.get_pin("vnb")
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self.objs.append(geometry.label("gnd", layer["pwellp"], pin.center()))
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self.objs.append(geometry.rectangle(layer["pwellp"],
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pin.ll(),
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pin.width(),
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pin.height()))
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except:
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pin = inst.get_pin("vnb")
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self.add_label("vdd", pin.layer, pin.center())
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