mirror of https://github.com/VLSIDA/OpenRAM.git
407 lines
16 KiB
Python
407 lines
16 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import math
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from openram import debug
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from openram import OPTS
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from openram.base import design
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from openram.base import vector
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from openram.base import logical_effort
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from openram.sram_factory import factory
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from .control_logic_base import control_logic_base
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class control_logic_delay(control_logic_base):
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"""
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Dynamically generated Control logic for the total SRAM circuit.
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Variant: delay-based
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"""
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def __init__(self, num_rows, words_per_row, word_size, spare_columns=None, sram=None, port_type="rw", name=""):
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""" Constructor """
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super().__init__(num_rows, words_per_row, word_size, spare_columns, sram, port_type, name)
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def add_pins(self):
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""" Add the pins to the control logic module. """
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self.add_pin_list(self.input_list + ["clk"], "INPUT")
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self.add_pin_list(self.output_list, "OUTPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def add_modules(self):
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""" Add all the required modules """
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self.dff = factory.create(module_type="dff_buf")
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dff_height = self.dff.height
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self.ctrl_dff_array = factory.create(module_type="dff_buf_array",
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rows=self.num_control_signals,
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columns=1)
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self.and2 = factory.create(module_type="pand2",
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size=12,
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height=dff_height)
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# clk_buf drives a flop for every address
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addr_flops = math.log(self.num_words, 2) + math.log(self.words_per_row, 2)
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# plus data flops and control flops
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num_flops = addr_flops + self.word_size + self.num_spare_cols + self.num_control_signals
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# each flop internally has a FO 5 approximately
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# plus about 5 fanouts for the control logic
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clock_fanout = 5 * num_flops + 5
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self.clk_buf_driver = factory.create(module_type="pdriver",
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fanout=clock_fanout,
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height=dff_height)
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# We will use the maximum since this same value is used to size the wl_en
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# and the p_en_bar drivers
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# max_fanout = max(self.num_rows, self.num_cols)
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# wl_en drives every row in the bank
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# this calculation is from the rbl control logic, it may not be optimal in this circuit
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size_list = [max(int(self.num_rows / 9), 1), max(int(self.num_rows / 3), 1)]
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self.wl_en_driver = factory.create(module_type="pdriver",
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size_list=size_list,
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height=dff_height)
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# wl_en_unbuf is the weak timing signal that feeds wl_en_driver
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self.wl_en_and = factory.create(module_type="pand2",
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size=1,
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height=dff_height)
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# w_en drives every write driver
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self.wen_and = factory.create(module_type="pand3",
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size=self.word_size + 8,
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height=dff_height)
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# s_en drives every sense amp
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self.sen_and3 = factory.create(module_type="pand3",
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size=self.word_size + self.num_spare_cols,
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height=dff_height)
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# used to generate inverted signals with low fanout
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self.inv = factory.create(module_type="pinv",
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size=1,
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height=dff_height)
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# p_en_bar drives every column in the bitcell array
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# but it is sized the same as the wl_en driver with
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# prepended 3 inverter stages to guarantee it is slower and odd polarity
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self.p_en_bar_driver = factory.create(module_type="pdriver",
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fanout=self.num_cols,
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height=dff_height)
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self.nand2 = factory.create(module_type="pnand2",
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height=dff_height)
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debug.check(OPTS.delay_chain_stages % 2,
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"Must use odd number of delay chain stages for inverting delay chain.")
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self.delay_chain=factory.create(module_type = "multi_delay_chain",
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fanout_list = 29 * [ OPTS.delay_chain_fanout_per_stage ], # TODO: generate this programatically
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pinout_list = [2, 12, 13, 15, 29]) # TODO: generate this list programatically
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def setup_signal_busses(self):
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""" Setup bus names, determine the size of the busses etc """
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# List of input control signals
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if self.port_type == "rw":
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self.input_list = ["csb", "web"]
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else:
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self.input_list = ["csb"]
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if self.port_type == "rw":
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self.dff_output_list = ["cs_bar", "cs", "we_bar", "we"]
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else:
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self.dff_output_list = ["cs_bar", "cs"]
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# list of output control signals (for making a vertical bus)
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if self.port_type == "rw":
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self.internal_bus_list = ["glitch2", "glitch3", "delay1", "delay2", "delay3", "delay4", "delay5", "gated_clk_bar", "gated_clk_buf", "we", "we_bar", "clk_buf", "cs"]
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else:
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self.internal_bus_list = ["glitch2", "glitch3", "delay1", "delay2", "delay3", "delay4", "delay5", "gated_clk_bar", "gated_clk_buf", "clk_buf", "cs"]
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# leave space for the bus plus one extra space
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self.internal_bus_width = (len(self.internal_bus_list) + 1) * self.m2_pitch
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# Outputs to the bank
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if self.port_type == "rw":
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self.output_list = ["s_en", "w_en"]
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elif self.port_type == "r":
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self.output_list = ["s_en"]
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else:
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self.output_list = ["w_en"]
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self.output_list.append("p_en_bar")
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self.output_list.append("wl_en")
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self.output_list.append("clk_buf")
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self.supply_list = ["vdd", "gnd"]
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def create_instances(self):
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""" Create all the instances """
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self.create_dffs()
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self.create_clk_buf_row()
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self.create_gated_clk_bar_row()
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self.create_gated_clk_buf_row()
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self.create_delay()
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self.create_glitches()
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self.create_wlen_row()
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if (self.port_type == "rw") or (self.port_type == "w"):
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self.create_wen_row()
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if (self.port_type == "rw") or (self.port_type == "r"):
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self.create_sen_row()
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self.create_pen_row()
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def place_logic_rows(self):
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row = 0
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self.place_clk_buf_row(row)
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row += 1
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self.place_gated_clk_bar_row(row)
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row += 1
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self.place_gated_clk_buf_row(row)
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row += 1
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if (self.port_type == "rw") or (self.port_type == "r"):
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self.place_sen_row(row)
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row += 1
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if (self.port_type == "rw") or (self.port_type == "w"):
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self.place_wen_row(row)
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row += 1
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self.place_pen_row(row)
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row += 1
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self.place_wlen_row(row)
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row += 1
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self.place_glitch2_row(row)
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row += 1
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self.place_glitch3_row(row)
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self.control_center_y = self.glitch3_nand_inst.uy() + self.m3_pitch
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def route_all(self):
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""" Routing between modules """
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self.route_rails()
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self.route_dffs()
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self.route_wlen()
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if (self.port_type == "rw") or (self.port_type == "w"):
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self.route_wen()
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if (self.port_type == "rw") or (self.port_type == "r"):
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self.route_sen()
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self.route_delay()
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self.route_pen()
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self.route_glitches()
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self.route_clk_buf()
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self.route_gated_clk_bar()
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self.route_gated_clk_buf()
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self.route_supplies()
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def create_delay(self):
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""" Create the delay chain """
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self.delay_inst=self.add_inst(name="multi_delay_chain",
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mod=self.delay_chain)
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self.connect_inst(["gated_clk_buf", "delay1", "delay2", "delay3", "delay4", "delay5", "vdd", "gnd"])
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def route_delay(self):
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# this is a bit of a hack because I would prefer to just name these pins delay in the layout
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# instead I have this which duplicates the out_pin naming logic from multi_delay_chain.py
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out_pins = ["out{}".format(str(pin)) for pin in self.delay_chain.pinout_list]
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delay_map = zip(["in", out_pins[0], out_pins[1], out_pins[2], out_pins[3], out_pins[4]], \
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["gated_clk_buf", "delay1", "delay2", "delay3", "delay4", "delay5"])
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self.connect_vertical_bus(delay_map,
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self.delay_inst,
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self.input_bus,
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self.m2_stack[::-1])
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# glitch{1-3} are internal timing signals based on different in/out
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# points on the delay chain for adjustable start time and duration
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def create_glitches(self):
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self.glitch1_nand_inst = self.add_inst(name="nand2_glitch1",
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mod=self.nand2)
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self.connect_inst(["delay1", "delay3", "glitch1", "vdd", "gnd"])
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self.glitch2_nand_inst = self.add_inst(name="nand2_glitch2",
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mod=self.nand2)
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self.connect_inst(["gated_clk_buf", "delay4", "glitch2", "vdd", "gnd"])
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self.glitch3_nand_inst = self.add_inst(name="nand2_glitch3",
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mod=self.nand2)
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self.connect_inst(["delay2", "delay5", "glitch3", "vdd", "gnd"])
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# glitch1 is placed in place_pen_row()
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def place_glitch2_row(self, row):
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x_offset = self.control_x_offset
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x_offset = self.place_util(self.glitch2_nand_inst, x_offset, row)
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self.row_end_inst.append(self.glitch2_nand_inst)
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def place_glitch3_row(self, row):
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x_offset = self.control_x_offset
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x_offset = self.place_util(self.glitch3_nand_inst, x_offset, row)
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self.row_end_inst.append(self.glitch3_nand_inst)
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def route_glitches(self):
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glitch2_map = zip(["A", "B", "Z"], ["gated_clk_buf", "delay4", "glitch2"])
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self.connect_vertical_bus(glitch2_map, self.glitch2_nand_inst, self.input_bus)
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glitch3_map = zip(["A", "B", "Z"], ["delay2", "delay5", "glitch3"])
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self.connect_vertical_bus(glitch3_map, self.glitch3_nand_inst, self.input_bus)
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def create_wlen_row(self):
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self.wl_en_unbuf_and_inst = self.add_inst(name="and_wl_en_unbuf",
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mod=self.wl_en_and)
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self.connect_inst(["cs", "glitch2", "wl_en_unbuf", "vdd", "gnd"])
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self.wl_en_driver_inst=self.add_inst(name="buf_wl_en",
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mod=self.wl_en_driver)
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self.connect_inst(["wl_en_unbuf", "wl_en", "vdd", "gnd"])
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def place_wlen_row(self, row):
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x_offset = self.control_x_offset
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x_offset = self.place_util(self.wl_en_unbuf_and_inst, x_offset, row)
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x_offset = self.place_util(self.wl_en_driver_inst, x_offset, row)
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self.row_end_inst.append(self.wl_en_driver_inst)
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def route_wlen(self):
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in_map = zip(["A", "B"], ["cs", "glitch2"])
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self.connect_vertical_bus(in_map, self.wl_en_unbuf_and_inst, self.input_bus)
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out_pin = self.wl_en_unbuf_and_inst.get_pin("Z")
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out_pos = out_pin.center()
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in_pin = self.wl_en_driver_inst.get_pin("A")
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in_pos = in_pin.center()
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mid1 = vector(out_pos.x, in_pos.y)
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self.add_path(out_pin.layer, [out_pos, mid1, in_pos])
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self.add_via_stack_center(from_layer=out_pin.layer,
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to_layer=in_pin.layer,
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offset=in_pin.center())
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self.connect_output(self.wl_en_driver_inst, "Z", "wl_en")
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def create_pen_row(self):
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self.p_en_bar_driver_inst=self.add_inst(name="buf_p_en_bar",
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mod=self.p_en_bar_driver)
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self.connect_inst(["glitch1", "p_en_bar", "vdd", "gnd"])
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def place_pen_row(self, row):
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x_offset = self.control_x_offset
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x_offset = self.place_util(self.glitch1_nand_inst, x_offset, row)
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x_offset = self.place_util(self.p_en_bar_driver_inst, x_offset, row)
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self.row_end_inst.append(self.p_en_bar_driver_inst)
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def route_pen(self):
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in_map = zip(["A", "B"], ["delay1", "delay3"])
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self.connect_vertical_bus(in_map, self.glitch1_nand_inst, self.input_bus)
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out_pin = self.glitch1_nand_inst.get_pin("Z") # same code here as wl_en, refactor?
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out_pos = out_pin.center()
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in_pin = self.p_en_bar_driver_inst.get_pin("A")
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in_pos = in_pin.center()
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mid1 = vector(in_pos.x, out_pos.y)
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self.add_path(out_pin.layer, [out_pos, mid1, in_pos])
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self.add_via_stack_center(from_layer=out_pin.layer,
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to_layer=in_pin.layer,
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offset=in_pin.center())
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self.connect_output(self.p_en_bar_driver_inst, "Z", "p_en_bar")
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def create_sen_row(self):
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if self.port_type=="rw":
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input_name = "we_bar"
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else:
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input_name = "cs"
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self.s_en_gate_inst = self.add_inst(name="and_s_en",
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mod=self.sen_and3)
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self.connect_inst(["glitch3", "gated_clk_bar", input_name, "s_en", "vdd", "gnd"])
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def place_sen_row(self, row):
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x_offset = self.control_x_offset
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x_offset = self.place_util(self.s_en_gate_inst, x_offset, row)
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self.row_end_inst.append(self.s_en_gate_inst)
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def route_sen(self):
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if self.port_type=="rw": # this is repeated many times in here, refactor?
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input_name = "we_bar"
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else:
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input_name = "cs"
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sen_map = zip(["A", "B", "C"], ["glitch3", "gated_clk_bar", input_name])
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self.connect_vertical_bus(sen_map, self.s_en_gate_inst, self.input_bus)
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self.connect_output(self.s_en_gate_inst, "Z", "s_en")
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def create_wen_row(self):
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self.glitch3_bar_inv_inst = self.add_inst(name="inv_glitch3_bar",
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mod=self.inv)
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self.connect_inst(["glitch3", "glitch3_bar", "vdd", "gnd"])
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if self.port_type == "rw":
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input_name = "we"
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else:
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input_name = "cs"
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self.w_en_gate_inst = self.add_inst(name="and_w_en",
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mod=self.wen_and)
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self.connect_inst([input_name, "glitch2", "glitch3_bar", "w_en", "vdd", "gnd"])
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def place_wen_row(self, row):
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x_offset = self.control_x_offset
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x_offset = self.place_util(self.glitch3_bar_inv_inst, x_offset, row)
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x_offset = self.place_util(self.w_en_gate_inst, x_offset, row)
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self.row_end_inst.append(self.w_en_gate_inst)
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def route_wen(self): # w_en comes from a 3and but one of the inputs needs to be inverted
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glitch3_map = zip(["A"], ["glitch3"])
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self.connect_vertical_bus(glitch3_map, self.glitch3_bar_inv_inst, self.input_bus)
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out_pin = self.glitch3_bar_inv_inst.get_pin("Z")
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out_pos = out_pin.center()
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in_pin = self.w_en_gate_inst.get_pin("C")
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in_pos = in_pin.center()
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mid1 = vector(in_pos.x, out_pos.y)
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self.add_path(out_pin.layer, [out_pos, mid1, in_pos])
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self.add_via_stack_center(from_layer=out_pin.layer,
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to_layer=in_pin.layer,
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offset=in_pos)
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if self.port_type == "rw":
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input_name = "we"
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else:
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input_name = "cs"
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# This is the second gate over, so it needs to be on M3
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wen_map = zip(["A", "B"], [input_name, "glitch2"])
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self.connect_vertical_bus(wen_map,
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self.w_en_gate_inst,
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self.input_bus,
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self.m2_stack[::-1])
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# The pins are on M1, so we need more vias as well
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a_pin = self.w_en_gate_inst.get_pin("A")
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self.add_via_stack_center(from_layer=a_pin.layer,
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to_layer="m3",
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offset=a_pin.center())
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b_pin = self.w_en_gate_inst.get_pin("B")
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self.add_via_stack_center(from_layer=b_pin.layer,
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to_layer="m3",
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offset=b_pin.center())
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self.connect_output(self.w_en_gate_inst, "Z", "w_en")
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