Jesse Cirimelli-Low 5222224936 route supplies from endcaps to power ring		2026-05-13 16:45:52 -07:00
..
base	power ring routing optimized, stretch crba pins to edge of power ring to avoid drc errors	2026-05-13 12:35:08 -07:00
characterizer	switch from conda to nix for tooling	2026-05-11 10:44:24 -07:00
datasheet	Update copyright year	2024-01-03 14:32:44 -08:00
drc	squash commits	2026-04-22 01:33:47 -07:00
gdsMill	compiler: gdsMill: Modernize codebase.	2026-04-17 13:14:03 +02:00
model_configs	Update copyright year	2024-01-03 14:32:44 -08:00
modules	route supplies from endcaps to power ring	2026-05-13 16:45:52 -07:00
router	Update copyright year	2024-01-03 14:32:44 -08:00
tests	technology switching working	2026-03-17 11:44:20 -07:00
verify	switch from conda to nix for tooling	2026-05-11 10:44:24 -07:00
Makefile	Change compiler name for unit tests	2022-11-06 14:05:08 -08:00
debug.py	Update copyright year	2024-01-03 14:32:44 -08:00
gen_stimulus.py	Update copyright year	2024-01-03 14:32:44 -08:00
globals.py	switch from conda to nix for tooling	2026-05-11 10:44:24 -07:00
model_data_util.py	Update copyright year	2024-01-03 14:32:44 -08:00
options.py	switch from conda to nix for tooling	2026-05-11 10:44:24 -07:00
rom.py	Add gf180mcu ROM example	2024-02-03 11:31:58 +01:00
rom_config.py	Update copyright year	2024-01-03 14:32:44 -08:00
run_profile.sh	Convert pin map to a set for faster membership.	2019-04-01 15:45:44 -07:00
sram.py	Update copyright year	2024-01-03 14:32:44 -08:00
sram_config.py	checkpoint from tt submission	2026-01-14 12:08:26 -08:00
sram_factory.py	Update copyright year	2024-01-03 14:32:44 -08:00
view_profile.py	Update copyright year	2024-01-03 14:32:44 -08:00