mirror of https://github.com/VLSIDA/OpenRAM.git
360 lines
14 KiB
Python
360 lines
14 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2022 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import math
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from openram import debug
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from openram.base import vector
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from openram.sram_factory import factory
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from openram import OPTS
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from .control_logic_base import control_logic_base
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class control_logic(control_logic_base):
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"""
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Dynamically generated Control logic for the total SRAM circuit.
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"""
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def __init__(self, num_rows, words_per_row, word_size, spare_columns=None, sram=None, port_type="rw", name=""):
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""" Constructor """
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super().__init__(num_rows, words_per_row, word_size, spare_columns, sram, port_type, name)
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def add_pins(self):
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""" Add the pins to the control logic module. """
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self.add_pin_list(self.input_list + ["clk"] + self.rbl_list, "INPUT")
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self.add_pin_list(self.output_list, "OUTPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def add_modules(self):
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""" Add all the required modules """
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self.dff = factory.create(module_type="dff_buf")
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dff_height = self.dff.height
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self.ctrl_dff_array = factory.create(module_type="dff_buf_array",
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rows=self.num_control_signals,
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columns=1)
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self.and2 = factory.create(module_type="pand2",
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size=12,
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height=dff_height)
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self.rbl_driver = factory.create(module_type="pbuf",
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size=self.num_cols,
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height=dff_height)
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# clk_buf drives a flop for every address
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addr_flops = math.log(self.num_words, 2) + math.log(self.words_per_row, 2)
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# plus data flops and control flops
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num_flops = addr_flops + self.word_size + self.num_spare_cols + self.num_control_signals
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# each flop internally has a FO 5 approximately
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# plus about 5 fanouts for the control logic
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clock_fanout = 5 * num_flops + 5
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self.clk_buf_driver = factory.create(module_type="pdriver",
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fanout=clock_fanout,
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height=dff_height)
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# We will use the maximum since this same value is used to size the wl_en
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# and the p_en_bar drivers
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# max_fanout = max(self.num_rows, self.num_cols)
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# wl_en drives every row in the bank
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# MRG 9/3/2021: Ensure that this is two stages to prevent race conditions with the write driver
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size_list = [max(int(self.num_rows / 9), 1), max(int(self.num_rows / 3), 1)]
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self.wl_en_driver = factory.create(module_type="pdriver",
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size_list=size_list,
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height=dff_height)
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# w_en drives every write driver
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self.wen_and = factory.create(module_type="pand3",
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size=self.word_size + 8,
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height=dff_height)
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# s_en drives every sense amp
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self.sen_and3 = factory.create(module_type="pand3",
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size=self.word_size + self.num_spare_cols,
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height=dff_height)
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# used to generate inverted signals with low fanout
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self.inv = factory.create(module_type="pinv",
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size=1,
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height=dff_height)
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# p_en_bar drives every column in the bitcell array
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# but it is sized the same as the wl_en driver with
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# prepended 3 inverter stages to guarantee it is slower and odd polarity
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self.p_en_bar_driver = factory.create(module_type="pdriver",
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fanout=self.num_cols,
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height=dff_height)
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self.nand2 = factory.create(module_type="pnand2",
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height=dff_height)
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debug.check(OPTS.delay_chain_stages % 2,
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"Must use odd number of delay chain stages for inverting delay chain.")
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self.delay_chain=factory.create(module_type="delay_chain",
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fanout_list = OPTS.delay_chain_stages * [ OPTS.delay_chain_fanout_per_stage ])
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def setup_signal_busses(self):
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""" Setup bus names, determine the size of the busses etc """
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# List of input control signals
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if self.port_type == "rw":
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self.input_list = ["csb", "web"]
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self.rbl_list = ["rbl_bl"]
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else:
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self.input_list = ["csb"]
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self.rbl_list = ["rbl_bl"]
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if self.port_type == "rw":
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self.dff_output_list = ["cs_bar", "cs", "we_bar", "we"]
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else:
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self.dff_output_list = ["cs_bar", "cs"]
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# list of output control signals (for making a vertical bus)
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if self.port_type == "rw":
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self.internal_bus_list = ["rbl_bl_delay_bar", "rbl_bl_delay", "gated_clk_bar", "gated_clk_buf", "we", "we_bar", "clk_buf", "cs"]
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elif self.port_type == "r":
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self.internal_bus_list = ["rbl_bl_delay_bar", "rbl_bl_delay", "gated_clk_bar", "gated_clk_buf", "clk_buf", "cs_bar", "cs"]
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else:
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self.internal_bus_list = ["rbl_bl_delay_bar", "rbl_bl_delay", "gated_clk_bar", "gated_clk_buf", "clk_buf", "cs"]
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# leave space for the bus plus one extra space
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self.internal_bus_width = (len(self.internal_bus_list) + 1) * self.m2_pitch
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# Outputs to the bank
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if self.port_type == "rw":
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self.output_list = ["s_en", "w_en"]
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elif self.port_type == "r":
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self.output_list = ["s_en"]
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else:
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self.output_list = ["w_en"]
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self.output_list.append("p_en_bar")
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self.output_list.append("wl_en")
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self.output_list.append("clk_buf")
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self.supply_list = ["vdd", "gnd"]
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def create_instances(self):
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""" Create all the instances """
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self.create_dffs()
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self.create_clk_buf_row()
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self.create_gated_clk_bar_row()
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self.create_gated_clk_buf_row()
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self.create_wlen_row()
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if (self.port_type == "rw") or (self.port_type == "w"):
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self.create_rbl_delay_row()
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self.create_wen_row()
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if (self.port_type == "rw") or (self.port_type == "r"):
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self.create_sen_row()
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self.create_delay()
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self.create_pen_row()
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def place_logic_rows(self):
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row = 0
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self.place_clk_buf_row(row)
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row += 1
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self.place_gated_clk_bar_row(row)
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row += 1
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self.place_gated_clk_buf_row(row)
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row += 1
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if (self.port_type == "rw") or (self.port_type == "r"):
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self.place_sen_row(row)
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row += 1
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if (self.port_type == "rw") or (self.port_type == "w"):
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self.place_wen_row(row)
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row += 1
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self.place_pen_row(row)
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row += 1
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if (self.port_type == "rw") or (self.port_type == "w"):
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self.place_rbl_delay_row(row)
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row += 1
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self.place_wlen_row(row)
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self.control_center_y = self.wl_en_inst.uy() + self.m3_pitch
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def route_all(self):
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""" Routing between modules """
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self.route_rails()
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self.route_dffs()
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self.route_wlen()
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if (self.port_type == "rw") or (self.port_type == "w"):
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self.route_rbl_delay()
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self.route_wen()
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if (self.port_type == "rw") or (self.port_type == "r"):
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self.route_sen()
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self.route_delay()
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self.route_pen()
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self.route_clk_buf()
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self.route_gated_clk_bar()
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self.route_gated_clk_buf()
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self.route_supplies()
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def create_delay(self):
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""" Create the delay chain """
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self.delay_inst=self.add_inst(name="delay_chain",
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mod=self.delay_chain)
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# rbl_bl_delay is asserted (1) when the bitline has been discharged
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self.connect_inst(["rbl_bl", "rbl_bl_delay", "vdd", "gnd"])
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def route_delay(self):
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out_pos = self.delay_inst.get_pin("out").center()
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# Connect to the rail level with the vdd rail
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# Use gated clock since it is in every type of control logic
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vdd_ypos = self.gated_clk_buf_inst.get_pin("vdd").cy() + self.m1_pitch
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in_pos = vector(self.input_bus["rbl_bl_delay"].cx(), vdd_ypos)
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mid1 = vector(out_pos.x, in_pos.y)
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self.add_wire(self.m1_stack, [out_pos, mid1, in_pos])
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self.add_via_center(layers=self.m1_stack,
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offset=in_pos)
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# Input from RBL goes to the delay line for futher delay
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self.copy_layout_pin(self.delay_inst, "in", "rbl_bl")
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def create_wlen_row(self):
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# input pre_p_en, output: wl_en
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self.wl_en_inst=self.add_inst(name="buf_wl_en",
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mod=self.wl_en_driver)
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self.connect_inst(["gated_clk_bar", "wl_en", "vdd", "gnd"])
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def place_wlen_row(self, row):
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x_offset = self.control_x_offset
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x_offset = self.place_util(self.wl_en_inst, x_offset, row)
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self.row_end_inst.append(self.wl_en_inst)
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def route_wlen(self):
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wlen_map = zip(["A"], ["gated_clk_bar"])
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self.connect_vertical_bus(wlen_map, self.wl_en_inst, self.input_bus)
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self.connect_output(self.wl_en_inst, "Z", "wl_en")
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def create_pen_row(self):
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self.p_en_bar_nand_inst=self.add_inst(name="nand_p_en_bar",
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mod=self.nand2)
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# We use the rbl_bl_delay here to ensure that the p_en is only asserted when the
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# bitlines have already been discharged. Otherwise, it is a combination loop.
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self.connect_inst(["gated_clk_buf", "rbl_bl_delay", "p_en_bar_unbuf", "vdd", "gnd"])
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self.p_en_bar_driver_inst=self.add_inst(name="buf_p_en_bar",
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mod=self.p_en_bar_driver)
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self.connect_inst(["p_en_bar_unbuf", "p_en_bar", "vdd", "gnd"])
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def place_pen_row(self, row):
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x_offset = self.control_x_offset
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x_offset = self.place_util(self.p_en_bar_nand_inst, x_offset, row)
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x_offset = self.place_util(self.p_en_bar_driver_inst, x_offset, row)
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self.row_end_inst.append(self.p_en_bar_driver_inst)
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def route_pen(self):
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in_map = zip(["A", "B"], ["gated_clk_buf", "rbl_bl_delay"])
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self.connect_vertical_bus(in_map, self.p_en_bar_nand_inst, self.input_bus)
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out_pin = self.p_en_bar_nand_inst.get_pin("Z")
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out_pos = out_pin.center()
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in_pin = self.p_en_bar_driver_inst.get_pin("A")
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in_pos = in_pin.center()
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mid1 = vector(in_pos.x, out_pos.y)
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self.add_path(out_pin.layer, [out_pos, mid1, in_pos])
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self.add_via_stack_center(from_layer=out_pin.layer,
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to_layer=in_pin.layer,
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offset=in_pin.center())
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self.connect_output(self.p_en_bar_driver_inst, "Z", "p_en_bar")
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def create_sen_row(self):
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""" Create the sense enable buffer. """
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if self.port_type=="rw":
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input_name = "we_bar"
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else:
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input_name = "cs"
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# GATE FOR S_EN
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self.s_en_gate_inst = self.add_inst(name="buf_s_en_and",
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mod=self.sen_and3)
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# s_en is asserted in the second half of the cycle during a read.
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# we also must wait until the bitline has been discharged enough for proper sensing
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# hence we use rbl_bl_delay as well.
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self.connect_inst(["rbl_bl_delay", "gated_clk_bar", input_name, "s_en", "vdd", "gnd"])
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def place_sen_row(self, row):
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x_offset = self.control_x_offset
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x_offset = self.place_util(self.s_en_gate_inst, x_offset, row)
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self.row_end_inst.append(self.s_en_gate_inst)
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def route_sen(self):
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if self.port_type=="rw":
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input_name = "we_bar"
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else:
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input_name = "cs"
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sen_map = zip(["A", "B", "C"], ["rbl_bl_delay", "gated_clk_bar", input_name])
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self.connect_vertical_bus(sen_map, self.s_en_gate_inst, self.input_bus)
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self.connect_output(self.s_en_gate_inst, "Z", "s_en")
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def create_rbl_delay_row(self):
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self.rbl_bl_delay_inv_inst = self.add_inst(name="rbl_bl_delay_inv",
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mod=self.inv)
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self.connect_inst(["rbl_bl_delay", "rbl_bl_delay_bar", "vdd", "gnd"])
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def place_rbl_delay_row(self, row):
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x_offset = self.control_x_offset
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x_offset = self.place_util(self.rbl_bl_delay_inv_inst, x_offset, row)
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self.row_end_inst.append(self.rbl_bl_delay_inv_inst)
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def route_rbl_delay(self):
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# Connect from delay line
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# Connect to rail
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self.route_output_to_bus_jogged(self.rbl_bl_delay_inv_inst, "rbl_bl_delay_bar")
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rbl_map = zip(["A"], ["rbl_bl_delay"])
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self.connect_vertical_bus(rbl_map, self.rbl_bl_delay_inv_inst, self.input_bus)
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def create_wen_row(self):
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# input: we (or cs) output: w_en
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if self.port_type == "rw":
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input_name = "we"
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else:
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# No we for write-only reports, so use cs
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input_name = "cs"
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# GATE THE W_EN
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self.w_en_gate_inst = self.add_inst(name="w_en_and",
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mod=self.wen_and)
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# Only drive the writes in the second half of the clock cycle during a write operation.
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self.connect_inst([input_name, "rbl_bl_delay_bar", "gated_clk_bar", "w_en", "vdd", "gnd"])
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def place_wen_row(self, row):
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x_offset = self.control_x_offset
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x_offset = self.place_util(self.w_en_gate_inst, x_offset, row)
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self.row_end_inst.append(self.w_en_gate_inst)
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def route_wen(self):
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if self.port_type == "rw":
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input_name = "we"
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else:
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# No we for write-only reports, so use cs
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input_name = "cs"
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wen_map = zip(["A", "B", "C"], [input_name, "rbl_bl_delay_bar", "gated_clk_bar"])
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self.connect_vertical_bus(wen_map, self.w_en_gate_inst, self.input_bus)
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self.connect_output(self.w_en_gate_inst, "Z", "w_en")
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