OpenRAM/compiler/verify
mrg 9a6ca328f6 Temporarily disable flatten and readonly in magic DRC 2021-01-06 09:42:56 -08:00
..
__init__.py Supply tree uses signal grid. PEP8 cleanup. 2020-12-21 13:51:50 -08:00
assura.py Output DRC and LVS run files to output directory. 2020-11-09 11:12:31 -08:00
calibre.py Fix copy gds/sp error with new relative paths 2020-12-11 10:22:35 -08:00
magic.py Temporarily disable flatten and readonly in magic DRC 2021-01-06 09:42:56 -08:00
none.py Supply tree uses signal grid. PEP8 cleanup. 2020-12-21 13:51:50 -08:00
run_script.py Decrease verbosity of script output 2020-12-01 17:12:17 -08:00