mirror of https://github.com/VLSIDA/OpenRAM.git
115 lines
3.4 KiB
Python
Executable File
115 lines
3.4 KiB
Python
Executable File
#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import unittest
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from testutils import *
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import sys, os
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sys.path.append(os.getenv("OPENRAM_HOME"))
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import globals
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from globals import OPTS
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import debug
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from sram_factory import factory
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#@unittest.skip("SKIPPING 04_pbitcell_test")
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class pbitcell_test(openram_test):
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def runTest(self):
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config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
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globals.init_openram(config_file)
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OPTS.num_rw_ports=1
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OPTS.num_w_ports=1
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OPTS.num_r_ports=1
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factory.reset()
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debug.info(2, "Bitcell with 1 of each port: read/write, write, and read")
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tx = factory.create(module_type="pbitcell")
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self.local_check(tx)
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OPTS.num_rw_ports=0
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OPTS.num_w_ports=1
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OPTS.num_r_ports=1
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factory.reset()
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debug.info(2, "Bitcell with 0 read/write ports")
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tx = factory.create(module_type="pbitcell")
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self.local_check(tx)
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OPTS.num_rw_ports=1
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OPTS.num_w_ports=0
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OPTS.num_r_ports=1
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factory.reset()
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debug.info(2, "Bitcell with 0 write ports")
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tx = factory.create(module_type="pbitcell")
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self.local_check(tx)
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OPTS.num_rw_ports=1
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OPTS.num_w_ports=1
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OPTS.num_r_ports=0
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factory.reset()
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debug.info(2, "Bitcell with 0 read ports")
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tx = factory.create(module_type="pbitcell")
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self.local_check(tx)
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OPTS.num_rw_ports=1
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OPTS.num_w_ports=0
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OPTS.num_r_ports=0
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factory.reset()
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debug.info(2, "Bitcell with 0 read ports and 0 write ports")
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tx = factory.create(module_type="pbitcell")
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self.local_check(tx)
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OPTS.num_rw_ports=2
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OPTS.num_w_ports=2
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OPTS.num_r_ports=2
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factory.reset()
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debug.info(2, "Bitcell with 2 of each port: read/write, write, and read")
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tx = factory.create(module_type="pbitcell")
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self.local_check(tx)
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OPTS.num_rw_ports=0
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OPTS.num_w_ports=2
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OPTS.num_r_ports=2
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factory.reset()
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debug.info(2, "Bitcell with 0 read/write ports")
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tx = factory.create(module_type="pbitcell")
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self.local_check(tx)
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OPTS.num_rw_ports=2
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OPTS.num_w_ports=0
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OPTS.num_r_ports=2
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factory.reset()
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debug.info(2, "Bitcell with 0 write ports")
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tx = factory.create(module_type="pbitcell")
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self.local_check(tx)
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OPTS.num_rw_ports=2
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OPTS.num_w_ports=2
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OPTS.num_r_ports=0
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factory.reset()
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debug.info(2, "Bitcell with 0 read ports")
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tx = factory.create(module_type="pbitcell")
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self.local_check(tx)
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OPTS.num_rw_ports=2
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OPTS.num_w_ports=0
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OPTS.num_r_ports=0
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factory.reset()
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debug.info(2, "Bitcell with 0 read ports and 0 write ports")
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tx = factory.create(module_type="pbitcell")
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self.local_check(tx)
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globals.end_openram()
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# run the test from the command line
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main(testRunner=debugTestRunner())
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