mirror of https://github.com/VLSIDA/OpenRAM.git
Comment out pbitcell tests. Add bitcell_1rw_1r test. Move bitcell horizontal routing to metal1. Extend precharge height for stacking. |
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|---|---|---|
| .. | ||
| pgate.py | ||
| pinv.py | ||
| pinvbuf.py | ||
| pnand2.py | ||
| pnand3.py | ||
| pnor2.py | ||
| precharge.py | ||
| ptx.py | ||
| single_level_column_mux.py | ||