mirror of https://github.com/VLSIDA/OpenRAM.git
132 lines
3.9 KiB
Python
132 lines
3.9 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from .bitcell_base_array import bitcell_base_array
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from base import vector
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from globals import OPTS
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from sram_factory import factory
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class rom_base_array(bitcell_base_array):
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def __init__(self, rows, cols, bitmap, name="", column_offset=0):
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super().__init__(name=name, rows=rows, cols=cols, column_offset=column_offset)
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self.data = bitmap
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self.create_all_bitline_names()
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self.create_all_wordline_names()
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self.create_netlist()
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self.create_layout()
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def create_netlist(self):
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self.add_modules()
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self.add_pins()
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self.create_instances()
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def create_layout(self):
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#self.add_layout_pins()
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self.place_ptx()
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self.route_supplies()
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#self.add_boundary()
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#self.DRC_LVS()
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#def add_pins(self):
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def add_boundary(self):
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self.width = self.nmos.width * self.column_size
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self.height = self.nmos.height * self.row_size
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super().add_boundary()
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def add_modules(self):
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self.nmos = factory.create(module_type="ptx", tx_type="nmos")
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def create_instances(self):
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self.cell_inst = {}
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self.current_row = 0
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for col in range(self.column_size):
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for row in range(self.row_size):
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name = "bit_r{0}_c{1}".format(row, col)
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if(self.data[col][row] == 1):
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self.cell_inst[row, col]=self.add_inst(name=name,
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mod=self.nmos)
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self.connect_inst(self.get_bitcell_pins(row, col))
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# If it is a "core" cell, it could be trimmed for sim time
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#if col>0 and col<self.column_size-1 and row>0 and row<self.row_size-1:
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# self.trim_insts.add(name)
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def place_ptx(self):
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self.cell_pos = {}
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for col in range(self.column_size):
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for row in range(self.row_size):
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if(self.data[col][row] == 1):
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cell_x = (self.nmos.width + 2 * self.nmos.active_contact_to_gate + self.nmos.contact_width) * col
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cell_y = (self.nmos.height + self.nmos.poly_extend_active) * row
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self.cell_pos[row, col] = self.nmos.active_offset.scale(1, 0) \
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+ vector(cell_x, cell_y)
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self.cell_inst[row, col].place(self.cell_pos[row, col])
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def create_all_bitline_names(self):
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for col in range(self.column_size):
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for port in self.all_ports:
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self.bitline_names[port].extend(["bl_{0}_{1}".format(port, col)])
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# Make a flat list too
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self.all_bitline_names = [x for sl in zip(*self.bitline_names) for x in sl]
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def get_bitcell_pins(self, row, col):
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bitcell_pins = []
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#drain pin
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if self.current_row == 0:
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bitcell_pins.append(self.bitline_names[0][col])
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else:
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bitcell_pins.append(self.get_current_bl_interconnect(col))
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#gate pin
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bitcell_pins.append(self.get_wordline_names()[row])
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#source pin
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if 1 not in self.data[col][row + 1:]:
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bitcell_pins.append("gnd")
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else:
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bitcell_pins.append(self.create_next_bl_interconnect(row, col))
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#body pin
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bitcell_pins.append("gnd")
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return bitcell_pins
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def create_next_bl_interconnect(self, row, col):
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self.current_row = row
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return "bli_{0}_{1}".format(row, col)
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def get_current_bl_interconnect(self, col):
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return "bli_{0}_{1}".format(self.current_row, col)
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