OpenRAM/compiler/sram
mrg b7c66d7e07 Changes to simplify metal preferred directions and pitches.
Changes to allow decoder height to be a 2x multiple of bitcell height.
Split of control logic tests.
Fixed track spacing in SRAM and channel router
PEP8 cleanup.
2020-05-10 11:32:45 -07:00
..
sram.py Fix lvs_write in sram class 2020-04-06 15:20:59 -07:00
sram_1bank.py Changes to simplify metal preferred directions and pitches. 2020-05-10 11:32:45 -07:00
sram_2bank.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
sram_base.py Changes to simplify metal preferred directions and pitches. 2020-05-10 11:32:45 -07:00
sram_config.py s8 gdsless netlist only working up to dff array 2020-02-09 21:37:09 -08:00