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OpenRAM/compiler/bitcells
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mrg b7c66d7e07 Changes to simplify metal preferred directions and pitches. 
Changes to allow decoder height to be a 2x multiple of bitcell height.
Split of control logic tests.
Fixed track spacing in SRAM and channel router
PEP8 cleanup.
 		2020-05-10 11:32:45 -07:00
..
bitcell.py Changes to simplify metal preferred directions and pitches. 2020-05-10 11:32:45 -07:00
bitcell_1rw_1r.py bitcell: Remove hardcoded signal pins 2020-02-12 15:37:51 +01:00
bitcell_1w_1r.py bitcell: Remove hardcoded signal pins 2020-02-12 15:37:51 +01:00
bitcell_base.py Refactor bitcell to bitcell_base. Pep8 format bitcells. 2019-10-06 01:08:23 +00:00
dummy_bitcell.py bitcell: Remove hardcoded signal pins 2020-02-12 15:37:51 +01:00
dummy_bitcell_1rw_1r.py bitcell: Remove hardcoded signal pins 2020-02-12 15:37:51 +01:00
dummy_bitcell_1w_1r.py bitcell: Remove hardcoded signal pins 2020-02-12 15:37:51 +01:00
dummy_pbitcell.py Add bbox for special DRC rule boundary 2019-12-05 23:14:25 +00:00
pbitcell.py Changes to simplify metal preferred directions and pitches. 2020-05-10 11:32:45 -07:00
replica_bitcell.py bitcell: Remove hardcoded signal pins 2020-02-12 15:37:51 +01:00
replica_bitcell_1rw_1r.py bitcell: Remove hardcoded signal pins 2020-02-12 15:37:51 +01:00
replica_bitcell_1w_1r.py bitcell: Remove hardcoded signal pins 2020-02-12 15:37:51 +01:00
replica_pbitcell.py Add bbox for special DRC rule boundary 2019-12-05 23:14:25 +00:00