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4a40e96f6d3522335f3ad7ed5a7cdc5c5d5f2ec9
OpenRAM/compiler/tests
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mrg 4a40e96f6d Control logic route changes. 
Move wl_en to top control signal.
Route wl_en directly to port_address.
Reorder input bus to bank.
2021-03-24 14:32:10 -07:00
..
configs
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golden
Add PDK layer names to tech file
2020-11-09 09:10:43 -08:00
00_code_format_check_test.py
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01_library_test.py
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03_contact_test.py
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03_path_test.py
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03_ptx_1finger_nmos_test.py
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03_ptx_1finger_pmos_test.py
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03_ptx_3finger_nmos_test.py
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03_ptx_3finger_pmos_test.py
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03_ptx_4finger_nmos_test.py
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03_ptx_4finger_pmos_test.py
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03_ptx_no_contacts_test.py
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03_wire_test.py
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04_and2_dec_test.py
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04_and3_dec_test.py
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04_and4_dec_test.py
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04_column_mux_1rw_1r_test.py
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04_column_mux_pbitcell_test.py
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04_column_mux_test.py
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04_dff_buf_test.py
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04_dummy_pbitcell_test.py
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04_pand2_test.py
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04_pand3_test.py
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04_pand4_test.py
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04_pbitcell_test.py
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04_pbuf_dec_8x_test.py
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04_pbuf_test.py
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04_pdriver_test.py
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04_pinv_1x_beta_test.py
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04_pinv_1x_test.py
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04_pinv_2x_test.py
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04_pinv_10x_test.py
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04_pinv_100x_test.py
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04_pinv_dec_1x_test.py
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04_pinvbuf_test.py
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04_pnand2_test.py
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04_pnand3_test.py
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04_pnand4_test.py
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04_pnor2_test.py
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04_precharge_1rw_1r_test.py
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04_precharge_pbitcell_test.py
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04_precharge_test.py
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04_pwrite_driver_test.py
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04_replica_pbitcell_test.py
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04_wordline_driver_test.py
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05_bitcell_array_1rw_1r_test.py
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05_bitcell_array_test.py
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05_dummy_array_test.py
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05_pbitcell_array_test.py
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06_hierarchical_decoder_1rw_1r_test.py
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06_hierarchical_decoder_pbitcell_test.py
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06_hierarchical_decoder_test.py
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06_hierarchical_predecode2x4_1rw_1r_test.py
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06_hierarchical_predecode2x4_pbitcell_test.py
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06_hierarchical_predecode2x4_test.py
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06_hierarchical_predecode3x8_1rw_1r_test.py
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06_hierarchical_predecode3x8_pbitcell_test.py
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06_hierarchical_predecode3x8_test.py
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06_hierarchical_predecode4x16_test.py
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07_column_mux_array_1rw_1r_test.py
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07_column_mux_array_pbitcell_test.py
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07_column_mux_array_test.py
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08_precharge_array_1rw_1r_test.py
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08_precharge_array_test.py
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08_wordline_buffer_array_test.py
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08_wordline_driver_array_1rw_1r_test.py
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08_wordline_driver_array_pbitcell_test.py
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08_wordline_driver_array_test.py
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09_sense_amp_array_1rw_1r_test.py
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09_sense_amp_array_spare_cols_test.py
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09_sense_amp_array_test_pbitcell.py
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09_sense_amp_array_test.py
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10_write_driver_array_1rw_1r_test.py
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10_write_driver_array_pbitcell_test.py
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10_write_driver_array_spare_cols_test.py
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10_write_driver_array_test.py
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10_write_driver_array_wmask_pbitcell_test.py
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10_write_driver_array_wmask_spare_cols_test.py
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10_write_driver_array_wmask_test.py
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10_write_mask_and_array_1rw_1r_test.py
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10_write_mask_and_array_pbitcell_test.py
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10_write_mask_and_array_test.py
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11_dff_array_test.py
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11_dff_buf_array_test.py
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12_tri_gate_array_test.py
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13_delay_chain_test.py
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14_replica_bitcell_array_1rw_1r_test.py
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14_replica_bitcell_array_test.py
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14_replica_column_1rw_1r_test.py
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14_replica_column_test.py
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14_replica_pbitcell_array_test.py
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15_global_bitcell_array_1rw_1r_test.py
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15_global_bitcell_array_test.py
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15_local_bitcell_array_1rw_1r_test.py
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15_local_bitcell_array_test.py
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16_control_logic_multiport_test.py
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16_control_logic_r_test.py
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16_control_logic_rw_test.py
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16_control_logic_w_test.py
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18_port_address_1rw_1r_test.py
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18_port_address_test.py
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18_port_data_1rw_1r_test.py
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18_port_data_spare_cols_test.py
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18_port_data_test.py
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18_port_data_wmask_1rw_1r_test.py
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18_port_data_wmask_test.py
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19_bank_select_pbitcell_test.py
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19_bank_select_test.py
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19_multi_bank_test.py
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19_pmulti_bank_test.py
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19_psingle_bank_test.py
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19_single_bank_1rw_1r_test.py
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19_single_bank_1w_1r_test.py
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19_single_bank_global_bitline.py
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19_single_bank_spare_cols_test.py
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19_single_bank_test.py
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19_single_bank_wmask_1rw_1r_test.py
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19_single_bank_wmask_test.py
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20_psram_1bank_2mux_1rw_1w_test.py
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20_psram_1bank_2mux_1rw_1w_wmask_test.py
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20_psram_1bank_2mux_1w_1r_test.py
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20_psram_1bank_2mux_test.py
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20_psram_1bank_4mux_1rw_1r_test.py
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20_sram_1bank_2mux_1rw_1r_spare_cols_test.py
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20_sram_1bank_2mux_1rw_1r_test.py
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20_sram_1bank_2mux_1w_1r_spare_cols_test.py
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20_sram_1bank_2mux_1w_1r_test.py
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20_sram_1bank_2mux_global_test.py
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20_sram_1bank_2mux_test.py
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20_sram_1bank_2mux_wmask_spare_cols_test.py
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20_sram_1bank_2mux_wmask_test.py
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20_sram_1bank_4mux_1rw_1r_test.py
Control logic route changes.
2021-03-24 14:32:10 -07:00
20_sram_1bank_4mux_test.py
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20_sram_1bank_8mux_1rw_1r_test.py
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20_sram_1bank_8mux_test.py
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20_sram_1bank_32b_1024_wmask_test.py
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20_sram_1bank_nomux_1rw_1r_spare_cols_test.py
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20_sram_1bank_nomux_1rw_1r_test.py
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20_sram_1bank_nomux_spare_cols_test.py
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20_sram_1bank_nomux_test.py
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20_sram_1bank_nomux_wmask_sparecols_test.py
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20_sram_1bank_nomux_wmask_test.py
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20_sram_2bank_test.py
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21_hspice_delay_test.py
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21_hspice_setuphold_test.py
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21_model_delay_test.py
Merge branch 'dev' into automated_analytical_model
2021-02-01 01:49:45 -08:00
21_ngspice_delay_extra_rows_test.py
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21_ngspice_delay_global_test.py
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21_ngspice_delay_test.py
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21_ngspice_setuphold_test.py
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22_psram_1bank_2mux_func_test.py
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22_psram_1bank_4mux_func_test.py
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22_psram_1bank_8mux_func_test.py
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22_psram_1bank_nomux_func_test.py
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22_sram_1bank_2mux_func_test.py
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22_sram_1bank_2mux_global_func_test.py
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22_sram_1bank_2mux_sparecols_func_test.py
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22_sram_1bank_4mux_func_test.py
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22_sram_1bank_8mux_func_test.py
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22_sram_1bank_nomux_1rw_1r_func_test.py
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22_sram_1bank_nomux_func_test.py
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22_sram_1bank_nomux_sparecols_func_test.py
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22_sram_1bank_wmask_1rw_1r_func_test.py
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22_sram_wmask_func_test.py
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23_lib_sram_linear_regression_test.py
Added test for linear regression model.
2020-12-14 14:37:53 -08:00
23_lib_sram_model_corners_test.py
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23_lib_sram_model_test.py
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23_lib_sram_prune_test.py
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23_lib_sram_test.py
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24_lef_sram_test.py
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25_verilog_sram_test.py
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26_hspice_pex_pinv_test.py
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26_ngspice_pex_pinv_test.py
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26_sram_pex_test.py
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30_openram_back_end_test.py
Update multithreaded regression.
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30_openram_front_end_test.py
Update multithreaded regression.
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50_riscv_func_test.py
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50_riscv_phys_test.py
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regress.py
Skywater changes.
2021-03-22 15:48:14 -07:00
skip_tests_sky130.txt
Default zom is None not negative.
2020-12-15 13:27:36 -08:00
sram_1rw_1r_tb.v
Convert capital names to lower case for consistency
2019-08-21 13:45:34 -07:00
sram_1rw_tb.v
Convert capital names to lower case for consistency
2019-08-21 13:45:34 -07:00
sram_1rw_wmask_tb.v
Convert capital names to lower case for consistency
2019-08-21 13:45:34 -07:00
testutils.py
Test new archive options for github actions.
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