mirror of https://github.com/VLSIDA/OpenRAM.git
45 lines
1.5 KiB
Python
45 lines
1.5 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import debug
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import design
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import utils
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from globals import OPTS
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from tech import parameter, drc, layer, GDS
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class s8_col_end(design.design):
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def __init__(self, version, name=""):
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super().__init__(name)
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pin_names = []
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type_list = []
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if version == "colend":
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self.name = "s8sram16x16_colenda"
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structure = "s8sram16x16_colenda\x00"
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elif version == "colend_p_cent":
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self.name = "s8sram16x16_colend_p_cent"
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structure = "s8sram16x16_colend_p_cent\x00"
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elif version == "colenda":
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self.name = "s8sram16x16_colenda"
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structure = "s8sram16x16_colenda\x00"
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elif version == "colenda_p_cent":
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self.name = "s8sram16x16_colenda_p_cent"
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structure = "s8sram16x16_colenda_p_cent"
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else:
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debug.error("Invalid type for col_end", -1)
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design.design.__init__(self, name=self.name)
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(self.width, self.height) = utils.get_libcell_size(self.name,
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GDS["unit"],
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layer["mem"],
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structure)
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pin_map = utils.get_libcell_pins(pin_names, self.name, GDS["unit"])
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