mirror of https://github.com/VLSIDA/OpenRAM.git
131 lines
4.9 KiB
Python
131 lines
4.9 KiB
Python
import sys
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import datetime
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import getpass
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import debug
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from globals import OPTS, print_time
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from sram_config import sram_config
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class sram():
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"""
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This is not a design module, but contains an SRAM design instance.
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It could later try options of number of banks and oganization to compare
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results.
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We can later add visualizer and other high-level functions as needed.
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"""
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def __init__(self, sram_config, name):
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sram_config.set_local_config(self)
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# reset the static duplicate name checker for unit tests
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# in case we create more than one SRAM
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from design import design
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design.name_map=[]
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debug.info(2, "create sram of size {0} with {1} num of words {2} banks".format(self.word_size,
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self.num_words,
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self.num_banks))
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start_time = datetime.datetime.now()
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self.name = name
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if self.num_banks == 1:
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from sram_1bank import sram_1bank as sram
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elif self.num_banks == 2:
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from sram_2bank import sram_2bank as sram
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else:
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debug.error("Invalid number of banks.",-1)
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self.s = sram(name, sram_config)
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self.s.create_netlist()
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if not OPTS.netlist_only:
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self.s.create_layout()
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if not OPTS.is_unit_test:
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print_time("SRAM creation", datetime.datetime.now(), start_time)
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def sp_write(self,name):
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self.s.sp_write(name)
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def gds_write(self,name):
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self.s.gds_write(name)
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def verilog_write(self,name):
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self.s.verilog_write(name)
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def save(self):
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""" Save all the output files while reporting time to do it as well. """
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if not OPTS.netlist_only:
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# Write the layout
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start_time = datetime.datetime.now()
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gdsname = OPTS.output_path + self.s.name + ".gds"
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print("GDS: Writing to {0}".format(gdsname))
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self.s.gds_write(gdsname)
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print_time("GDS", datetime.datetime.now(), start_time)
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# Create a LEF physical model
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start_time = datetime.datetime.now()
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lefname = OPTS.output_path + self.s.name + ".lef"
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print("LEF: Writing to {0}".format(lefname))
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self.s.lef_write(lefname)
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print_time("LEF", datetime.datetime.now(), start_time)
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# Save the spice file
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start_time = datetime.datetime.now()
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spname = OPTS.output_path + self.s.name + ".sp"
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print("SP: Writing to {0}".format(spname))
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self.s.sp_write(spname)
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print_time("Spice writing", datetime.datetime.now(), start_time)
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# Save the extracted spice file
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if OPTS.use_pex:
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import verify
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start_time = datetime.datetime.now()
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# Output the extracted design if requested
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sp_file = OPTS.output_path + "temp_pex.sp"
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verify.run_pex(self.s.name, gdsname, spname, output=sp_file)
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print_time("Extraction", datetime.datetime.now(), start_time)
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else:
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# Use generated spice file for characterization
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sp_file = spname
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# Characterize the design
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start_time = datetime.datetime.now()
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from characterizer import lib
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print("LIB: Characterizing... ")
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if OPTS.analytical_delay:
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print("Using analytical delay models (no characterization)")
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else:
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if OPTS.spice_name!="":
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print("Performing simulation-based characterization with {}".format(OPTS.spice_name))
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if OPTS.trim_netlist:
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print("Trimming netlist to speed up characterization.")
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lib(out_dir=OPTS.output_path, sram=self.s, sp_file=sp_file)
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print_time("Characterization", datetime.datetime.now(), start_time)
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# Write the config file
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start_time = datetime.datetime.now()
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from shutil import copyfile
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copyfile(OPTS.config_file + '.py', OPTS.output_path + OPTS.output_name + '.py')
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print("Config: Writing to {0}".format(OPTS.output_path + OPTS.output_name + '.py'))
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print_time("Config", datetime.datetime.now(), start_time)
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# Write the datasheet
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start_time = datetime.datetime.now()
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from datasheet_gen import datasheet_gen
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dname = OPTS.output_path + self.s.name + ".html"
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print("Datasheet: Writing to {0}".format(dname))
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datasheet_gen.datasheet_write(self.s,dname)
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print_time("Datasheet", datetime.datetime.now(), start_time)
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# Write a verilog model
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start_time = datetime.datetime.now()
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vname = OPTS.output_path + self.s.name + ".v"
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print("Verilog: Writing to {0}".format(vname))
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self.s.verilog_write(vname)
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print_time("Verilog", datetime.datetime.now(), start_time)
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