mirror of https://github.com/VLSIDA/OpenRAM.git
144 lines
4.8 KiB
Python
144 lines
4.8 KiB
Python
import debug
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from tech import drc
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from math import log
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from vector import vector
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from globals import OPTS
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from pinv import pinv
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import pgate
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class pbuf(pgate.pgate):
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"""
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This is a simple buffer used for driving loads.
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"""
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from importlib import reload
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c = reload(__import__(OPTS.bitcell))
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bitcell = getattr(c, OPTS.bitcell)
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unique_id = 1
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def __init__(self, size=4, height=None, name=""):
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self.stage_effort = 4
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self.size = size
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self.height = height
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if name=="":
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name = "pbuf_{0}_{1}".format(self.size, pbuf.unique_id)
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pbuf.unique_id += 1
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pgate.pgate.__init__(self, name, height)
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debug.info(1, "creating {0} with size of {1}".format(self.name,self.size))
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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self.add_pins()
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self.create_modules()
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self.create_insts()
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def create_layout(self):
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self.width = self.inv1.width + self.inv2.width
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self.place_insts()
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self.add_wires()
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self.add_layout_pins()
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def add_pins(self):
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self.add_pin("A")
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self.add_pin("Z")
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self.add_pin("vdd")
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self.add_pin("gnd")
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def create_modules(self):
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# Shield the cap, but have at least a stage effort of 4
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input_size = max(1,int(self.size/self.stage_effort))
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self.inv1 = pinv(size=input_size, height=self.height)
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self.add_mod(self.inv1)
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self.inv2 = pinv(size=self.size, height=self.height)
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self.add_mod(self.inv2)
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def create_insts(self):
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self.inv1_inst=self.add_inst(name="buf_inv1",
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mod=self.inv1)
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self.connect_inst(["A", "zb_int", "vdd", "gnd"])
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self.inv2_inst=self.add_inst(name="buf_inv2",
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mod=self.inv2)
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self.connect_inst(["zb_int", "Z", "vdd", "gnd"])
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def place_insts(self):
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# Add INV1 to the right
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self.inv1_inst.place(vector(0,0))
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# Add INV2 to the right
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self.inv2_inst.place(vector(self.inv1_inst.rx(),0))
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def add_wires(self):
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# inv1 Z to inv2 A
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z1_pin = self.inv1_inst.get_pin("Z")
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a2_pin = self.inv2_inst.get_pin("A")
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mid_point = vector(z1_pin.cx(), a2_pin.cy())
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self.add_path("metal1", [z1_pin.center(), mid_point, a2_pin.center()])
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def add_layout_pins(self):
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# Continous vdd rail along with label.
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vdd_pin=self.inv1_inst.get_pin("vdd")
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self.add_layout_pin(text="vdd",
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layer="metal1",
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offset=vdd_pin.ll().scale(0,1),
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width=self.width,
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height=vdd_pin.height())
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# Continous gnd rail along with label.
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gnd_pin=self.inv1_inst.get_pin("gnd")
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self.add_layout_pin(text="gnd",
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layer="metal1",
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offset=gnd_pin.ll().scale(0,1),
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width=self.width,
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height=vdd_pin.height())
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z_pin = self.inv2_inst.get_pin("Z")
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self.add_layout_pin_rect_center(text="Z",
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layer=z_pin.layer,
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offset=z_pin.center(),
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width=z_pin.width(),
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height=z_pin.height())
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a_pin = self.inv1_inst.get_pin("A")
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self.add_layout_pin_rect_center(text="A",
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layer=a_pin.layer,
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offset=a_pin.center(),
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width=a_pin.width(),
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height=a_pin.height())
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def analytical_delay(self, slew, load=0.0):
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""" Calculate the analytical delay of DFF-> INV -> INV """
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inv1_delay = self.inv1.analytical_delay(slew=slew, load=self.inv2.input_load())
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inv2_delay = self.inv2.analytical_delay(slew=inv1_delay.slew, load=load)
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return inv1_delay + inv2_delay
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def get_output_stage_efforts(self, external_cout, inp_is_rise=False):
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"""Get the stage efforts of the A -> Z path"""
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stage_effort_list = []
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stage1_cout = self.inv2.get_cin()
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stage1 = self.inv1.get_effort_stage(stage1_cout, inp_is_rise)
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stage_effort_list.append(stage1)
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last_stage_is_rise = stage1.is_rise
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stage2 = self.inv2.get_effort_stage(external_cout, last_stage_is_rise)
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stage_effort_list.append(stage2)
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return stage_effort_list
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def get_cin(self):
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"""Returns the relative capacitance of the input"""
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input_cin = self.inv1.get_cin()
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return input_cin |