mirror of https://github.com/VLSIDA/OpenRAM.git
494 lines
25 KiB
Python
494 lines
25 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import debug
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from vector import vector
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from sram_base import sram_base
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from contact import m2_via
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class sram_1bank(sram_base):
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"""
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Procedures specific to a one bank SRAM.
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"""
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def __init__(self, name, sram_config):
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sram_base.__init__(self, name, sram_config)
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def create_modules(self):
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"""
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This adds the modules for a single bank SRAM with control
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logic.
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"""
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self.bank_inst=self.create_bank(0)
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self.control_logic_insts = self.create_control_logic()
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self.row_addr_dff_insts = self.create_row_addr_dff()
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if self.col_addr_dff:
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self.col_addr_dff_insts = self.create_col_addr_dff()
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if self.write_size:
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self.wmask_dff_insts = self.create_wmask_dff()
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self.data_dff_insts = self.create_data_dff()
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else:
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self.data_dff_insts = self.create_data_dff()
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def place_instances(self):
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"""
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This places the instances for a single bank SRAM with control
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logic and up to 2 ports.
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"""
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# No orientation or offset
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self.place_bank(self.bank_inst, [0, 0], 1, 1)
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# The control logic is placed such that the vertical center (between the delay/RBL and
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# the actual control logic is aligned with the vertical center of the bank (between
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# the sense amps/column mux and cell array)
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# The x-coordinate is placed to allow a single clock wire (plus an extra pitch)
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# up to the row address DFFs.
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control_pos = [None] * len(self.all_ports)
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row_addr_pos = [None] * len(self.all_ports)
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col_addr_pos = [None] * len(self.all_ports)
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wmask_pos = [None] * len(self.all_ports)
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data_pos = [None] * len(self.all_ports)
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if self.write_size:
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max_gap_size = self.m3_pitch * self.word_size + 2 * self.m1_pitch
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max_gap_size_wmask = self.m2_pitch * max(self.num_wmasks + 1, self.col_addr_size + 1) + 2 * self.m1_pitch
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else:
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# This is M2 pitch even though it is on M1 to help stem via spacings on the trunk
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# The M1 pitch is for supply rail spacings
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max_gap_size = self.m2_pitch * max(self.word_size + 1,self.col_addr_size + 1) + 2 * self.m1_pitch
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# Port 0
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port = 0
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if port in self.write_ports:
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if self.write_size:
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# Add the write mask flops below the write mask AND array.
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wmask_pos[port] = vector(self.bank.bank_array_ll.x,
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-max_gap_size_wmask - self.dff.height)
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self.wmask_dff_insts[port].place(wmask_pos[port])
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# Add the data flops below the write mask flops.
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data_pos[port] = vector(self.bank.bank_array_ll.x,
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-max_gap_size - max_gap_size_wmask - 2 * self.dff.height)
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self.data_dff_insts[port].place(data_pos[port])
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else:
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# Add the data flops below the bank to the right of the lower-left of bank array
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# This relies on the lower-left of the array of the bank
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# decoder in upper left, bank in upper right, sensing in lower right.
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# These flops go below the sensing and leave a gap to channel route to the
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# sense amps.
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if port in self.write_ports:
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data_pos[port] = vector(self.bank.bank_array_ll.x,
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-max_gap_size - self.dff.height)
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self.data_dff_insts[port].place(data_pos[port])
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else:
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wmask_pos[port] = vector(self.bank.bank_array_ll.x, 0)
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data_pos[port] = vector(self.bank.bank_array_ll.x, 0)
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# Add the col address flops below the bank to the left of the lower-left of bank array
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if self.col_addr_dff:
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if self.write_size:
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col_addr_pos[port] = vector(self.bank.bank_array_ll.x - self.col_addr_dff_insts[port].width - self.bank.m2_gap,
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-max_gap_size_wmask - self.col_addr_dff_insts[port].height)
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else:
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col_addr_pos[port] = vector(self.bank.bank_array_ll.x - self.col_addr_dff_insts[port].width - self.bank.m2_gap,
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-max_gap_size - self.col_addr_dff_insts[port].height)
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self.col_addr_dff_insts[port].place(col_addr_pos[port])
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else:
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col_addr_pos[port] = vector(self.bank.bank_array_ll.x, 0)
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# This includes 2 M2 pitches for the row addr clock line.
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control_pos[port] = vector(-self.control_logic_insts[port].width - 2 * self.m2_pitch,
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self.bank.bank_array_ll.y - self.control_logic_insts[port].mod.control_logic_center.y - 2 * self.bank.m2_gap)
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self.control_logic_insts[port].place(control_pos[port])
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# The row address bits are placed above the control logic aligned on the right.
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x_offset = self.control_logic_insts[port].rx() - self.row_addr_dff_insts[port].width
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# It is above the control logic but below the top of the bitcell array
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y_offset = max(self.control_logic_insts[port].uy(), self.bank_inst.uy() - self.row_addr_dff_insts[port].height)
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row_addr_pos[port] = vector(x_offset, y_offset)
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self.row_addr_dff_insts[port].place(row_addr_pos[port])
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if len(self.all_ports)>1:
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# Port 1
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port = 1
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if port in self.write_ports:
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if self.write_size:
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# Add the write mask flops below the write mask AND array.
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wmask_pos[port] = vector(self.bank.bank_array_ur.x - self.wmask_dff_insts[port].width,
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self.bank.height + max_gap_size_wmask + self.dff.height)
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self.wmask_dff_insts[port].place(wmask_pos[port], mirror="MX")
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# Add the data flops below the write mask flops
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data_pos[port] = vector(self.bank.bank_array_ur.x - self.data_dff_insts[port].width,
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self.bank.height + max_gap_size_wmask + max_gap_size + 2 * self.dff.height)
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self.data_dff_insts[port].place(data_pos[port], mirror="MX")
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else:
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# Add the data flops above the bank to the left of the upper-right of bank array
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# This relies on the upper-right of the array of the bank
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# decoder in upper left, bank in upper right, sensing in lower right.
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# These flops go below the sensing and leave a gap to channel route to the
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# sense amps.
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data_pos[port] = vector(self.bank.bank_array_ur.x - self.data_dff_insts[port].width,
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self.bank.height + max_gap_size + self.dff.height)
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self.data_dff_insts[port].place(data_pos[port], mirror="MX")
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# Add the col address flops above the bank to the right of the upper-right of bank array
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if self.col_addr_dff:
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if self.write_size:
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col_addr_pos[port] = vector(self.bank.bank_array_ur.x + self.bank.m2_gap,
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self.bank.height + max_gap_size_wmask + self.dff.height)
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else:
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col_addr_pos[port] = vector(self.bank.bank_array_ur.x + self.bank.m2_gap,
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self.bank.height + max_gap_size + self.dff.height)
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self.col_addr_dff_insts[port].place(col_addr_pos[port], mirror="MX")
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else:
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col_addr_pos[port] = self.bank_inst.ur()
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# This includes 2 M2 pitches for the row addr clock line
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control_pos[port] = vector(self.bank_inst.rx() + self.control_logic_insts[port].width + 2 * self.m2_pitch,
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self.bank.bank_array_ur.y + self.control_logic_insts[port].height - \
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(self.control_logic_insts[port].height - self.control_logic_insts[port].mod.control_logic_center.y)
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+ 2 * self.bank.m2_gap)
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self.control_logic_insts[port].place(control_pos[port], mirror="XY")
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# The row address bits are placed above the control logic aligned on the left.
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x_offset = control_pos[port].x - self.control_logic_insts[port].width + self.row_addr_dff_insts[port].width
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# It is below the control logic but below the bottom of the bitcell array
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y_offset = min(self.control_logic_insts[port].by(), self.bank_inst.by() + self.row_addr_dff_insts[port].height)
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row_addr_pos[port] = vector(x_offset, y_offset)
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self.row_addr_dff_insts[port].place(row_addr_pos[port], mirror="XY")
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def add_layout_pins(self):
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"""
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Add the top-level pins for a single bank SRAM with control.
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"""
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for port in self.all_ports:
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# Connect the control pins as inputs
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for signal in self.control_logic_inputs[port] + ["clk"]:
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self.copy_layout_pin(self.control_logic_insts[port],
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signal,
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signal + "{}".format(port))
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if port in self.read_ports:
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for bit in range(self.word_size):
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self.copy_layout_pin(self.bank_inst,
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"dout{0}_{1}".format(port, bit),
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"dout{0}[{1}]".format(port, bit))
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# Lower address bits
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for bit in range(self.col_addr_size):
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self.copy_layout_pin(self.col_addr_dff_insts[port],
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"din_{}".format(bit),
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"addr{0}[{1}]".format(port, bit))
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# Upper address bits
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for bit in range(self.row_addr_size):
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self.copy_layout_pin(self.row_addr_dff_insts[port],
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"din_{}".format(bit),
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"addr{0}[{1}]".format(port, bit + self.col_addr_size))
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if port in self.write_ports:
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for bit in range(self.word_size):
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self.copy_layout_pin(self.data_dff_insts[port],
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"din_{}".format(bit),
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"din{0}[{1}]".format(port, bit))
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if self.write_size:
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for bit in range(self.num_wmasks):
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self.copy_layout_pin(self.wmask_dff_insts[port],
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"din_{}".format(bit),
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"wmask{0}[{1}]".format(port, bit))
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def route_layout(self):
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""" Route a single bank SRAM """
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self.add_layout_pins()
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self.route_clk()
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self.route_control_logic()
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self.route_row_addr_dff()
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if self.col_addr_dff:
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self.route_col_addr_dff()
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self.route_data_dff()
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if self.write_size:
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self.route_wmask_dff()
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def route_clk(self):
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""" Route the clock network """
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# This is the actual input to the SRAM
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for port in self.all_ports:
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self.copy_layout_pin(self.control_logic_insts[port], "clk", "clk{}".format(port))
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# Connect all of these clock pins to the clock in the central bus
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# This is something like a "spine" clock distribution. The two spines
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# are clk_buf and clk_buf_bar
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control_clk_buf_pin = self.control_logic_insts[port].get_pin("clk_buf")
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control_clk_buf_pos = control_clk_buf_pin.center()
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# This uses a metal2 track to the right (for port0) of the control/row addr DFF
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# to route vertically. For port1, it is to the left.
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row_addr_clk_pin = self.row_addr_dff_insts[port].get_pin("clk")
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if port%2:
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control_clk_buf_pos = control_clk_buf_pin.lc()
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row_addr_clk_pos = row_addr_clk_pin.lc()
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mid1_pos = vector(self.row_addr_dff_insts[port].lx() - self.m2_pitch,
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row_addr_clk_pos.y)
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else:
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control_clk_buf_pos = control_clk_buf_pin.rc()
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row_addr_clk_pos = row_addr_clk_pin.rc()
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mid1_pos = vector(self.row_addr_dff_insts[port].rx() + self.m2_pitch,
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row_addr_clk_pos.y)
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# This is the steiner point where the net branches out
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clk_steiner_pos = vector(mid1_pos.x, control_clk_buf_pos.y)
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self.add_path("m1", [control_clk_buf_pos, clk_steiner_pos])
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self.add_via_center(layers=self.m1_stack,
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offset=clk_steiner_pos)
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# Note, the via to the control logic is taken care of above
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self.add_wire(("m3", "via2", "m2"),
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[row_addr_clk_pos, mid1_pos, clk_steiner_pos])
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if self.col_addr_dff:
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dff_clk_pin = self.col_addr_dff_insts[port].get_pin("clk")
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dff_clk_pos = dff_clk_pin.center()
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mid_pos = vector(clk_steiner_pos.x, dff_clk_pos.y)
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self.add_wire(("m3", "via2", "m2"),
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[dff_clk_pos, mid_pos, clk_steiner_pos])
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if port in self.write_ports:
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data_dff_clk_pin = self.data_dff_insts[port].get_pin("clk")
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data_dff_clk_pos = data_dff_clk_pin.center()
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mid_pos = vector(clk_steiner_pos.x, data_dff_clk_pos.y)
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# In some designs, the steiner via will be too close to the mid_pos via
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# so make the wire as wide as the contacts
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self.add_path("m2",
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[mid_pos, clk_steiner_pos],
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width=max(m2_via.width, m2_via.height))
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self.add_wire(("m3", "via2", "m2"),
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[data_dff_clk_pos, mid_pos, clk_steiner_pos])
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if self.write_size:
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wmask_dff_clk_pin = self.wmask_dff_insts[port].get_pin("clk")
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wmask_dff_clk_pos = wmask_dff_clk_pin.center()
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mid_pos = vector(clk_steiner_pos.x, wmask_dff_clk_pos.y)
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# In some designs, the steiner via will be too close to the mid_pos via
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# so make the wire as wide as the contacts
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self.add_path("m2", [mid_pos, clk_steiner_pos], width=max(m2_via.width, m2_via.height))
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self.add_wire(("m3", "via2", "m2"), [wmask_dff_clk_pos, mid_pos, clk_steiner_pos])
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def route_control_logic(self):
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""" Route the control logic pins that are not inputs """
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for port in self.all_ports:
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for signal in self.control_logic_outputs[port]:
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# The clock gets routed separately and is not a part of the bank
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if "clk" in signal:
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continue
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src_pin = self.control_logic_insts[port].get_pin(signal)
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dest_pin = self.bank_inst.get_pin(signal + "{}".format(port))
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self.connect_vbus_m2m3(src_pin, dest_pin)
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for port in self.all_ports:
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# Only input (besides pins) is the replica bitline
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src_pin = self.control_logic_insts[port].get_pin("rbl_bl")
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dest_pin = self.bank_inst.get_pin("rbl_bl{}".format(port))
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self.connect_hbus_m2m3(src_pin, dest_pin)
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def route_row_addr_dff(self):
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""" Connect the output of the row flops to the bank pins """
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for port in self.all_ports:
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for bit in range(self.row_addr_size):
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flop_name = "dout_{}".format(bit)
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bank_name = "addr{0}_{1}".format(port, bit + self.col_addr_size)
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flop_pin = self.row_addr_dff_insts[port].get_pin(flop_name)
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bank_pin = self.bank_inst.get_pin(bank_name)
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flop_pos = flop_pin.center()
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bank_pos = bank_pin.center()
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mid_pos = vector(bank_pos.x, flop_pos.y)
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self.add_wire(("m3", "via2", "m2"),
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[flop_pos, mid_pos, bank_pos])
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self.add_via_center(layers=self.m2_stack,
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offset=flop_pos)
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def route_col_addr_dff(self):
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""" Connect the output of the col flops to the bank pins """
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for port in self.all_ports:
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if port%2:
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offset = self.col_addr_dff_insts[port].ll() - vector(0, (self.col_addr_size + 2) * self.m1_pitch)
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else:
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offset = self.col_addr_dff_insts[port].ul() + vector(0, 2 * self.m1_pitch)
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bus_names = ["addr_{}".format(x) for x in range(self.col_addr_size)]
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col_addr_bus_offsets = self.create_horizontal_bus(layer="m1",
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pitch=self.m1_pitch,
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offset=offset,
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names=bus_names,
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length=self.col_addr_dff_insts[port].width)
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dff_names = ["dout_{}".format(x) for x in range(self.col_addr_size)]
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data_dff_map = zip(dff_names, bus_names)
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self.connect_horizontal_bus(data_dff_map, self.col_addr_dff_insts[port], col_addr_bus_offsets)
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bank_names = ["addr{0}_{1}".format(port, x) for x in range(self.col_addr_size)]
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data_bank_map = zip(bank_names, bus_names)
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self.connect_horizontal_bus(data_bank_map, self.bank_inst, col_addr_bus_offsets)
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def route_data_dff(self):
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""" Connect the output of the data flops to the write driver """
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# This is where the channel will start (y-dimension at least)
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for port in self.write_ports:
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if self.write_size:
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if port % 2:
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offset = self.data_dff_insts[port].ll() - vector(0, (self.word_size + 2) * self.m3_pitch)
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else:
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offset = self.data_dff_insts[port].ul() + vector(0, 2 * self.m3_pitch)
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else:
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if port % 2:
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offset = self.data_dff_insts[port].ll() - vector(0, (self.word_size + 2) * self.m1_pitch)
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else:
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offset = self.data_dff_insts[port].ul() + vector(0, 2 * self.m1_pitch)
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dff_names = ["dout_{}".format(x) for x in range(self.word_size)]
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dff_pins = [self.data_dff_insts[port].get_pin(x) for x in dff_names]
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if self.write_size:
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for x in dff_names:
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pin_offset = self.data_dff_insts[port].get_pin(x).center()
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self.add_via_center(layers=self.m1_stack,
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offset=pin_offset,
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directions=("V", "V"))
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self.add_via_center(layers=self.m2_stack,
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offset=pin_offset)
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self.add_via_center(layers=self.m3_stack,
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offset=pin_offset)
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bank_names = ["din{0}_{1}".format(port, x) for x in range(self.word_size)]
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bank_pins = [self.bank_inst.get_pin(x) for x in bank_names]
|
|
if self.write_size:
|
|
for x in bank_names:
|
|
if port % 2:
|
|
pin_offset = self.bank_inst.get_pin(x).uc()
|
|
else:
|
|
pin_offset = self.bank_inst.get_pin(x).bc()
|
|
self.add_via_center(layers=self.m1_stack,
|
|
offset=pin_offset)
|
|
self.add_via_center(layers=self.m2_stack,
|
|
offset=pin_offset)
|
|
self.add_via_center(layers=self.m3_stack,
|
|
offset=pin_offset)
|
|
|
|
route_map = list(zip(bank_pins, dff_pins))
|
|
if self.write_size:
|
|
layer_stack = self.m3_stack
|
|
else:
|
|
layer_stack = self.m1_stack
|
|
self.create_horizontal_channel_route(netlist=route_map,
|
|
offset=offset,
|
|
layer_stack=layer_stack)
|
|
|
|
def route_wmask_dff(self):
|
|
""" Connect the output of the wmask flops to the write mask AND array """
|
|
# This is where the channel will start (y-dimension at least)
|
|
for port in self.write_ports:
|
|
if port % 2:
|
|
offset = self.wmask_dff_insts[port].ll() - vector(0, (self.num_wmasks + 2) * self.m1_pitch)
|
|
else:
|
|
offset = self.wmask_dff_insts[port].ul() + vector(0, 2 * self.m1_pitch)
|
|
|
|
dff_names = ["dout_{}".format(x) for x in range(self.num_wmasks)]
|
|
dff_pins = [self.wmask_dff_insts[port].get_pin(x) for x in dff_names]
|
|
for x in dff_names:
|
|
offset_pin = self.wmask_dff_insts[port].get_pin(x).center()
|
|
self.add_via_center(layers=self.m1_stack,
|
|
offset=offset_pin,
|
|
directions=("V", "V"))
|
|
|
|
bank_names = ["bank_wmask{0}_{1}".format(port, x) for x in range(self.num_wmasks)]
|
|
bank_pins = [self.bank_inst.get_pin(x) for x in bank_names]
|
|
for x in bank_names:
|
|
offset_pin = self.bank_inst.get_pin(x).center()
|
|
self.add_via_center(layers=self.m1_stack,
|
|
offset=offset_pin)
|
|
|
|
route_map = list(zip(bank_pins, dff_pins))
|
|
self.create_horizontal_channel_route(netlist=route_map,
|
|
offset=offset,
|
|
layer_stack=self.m1_stack)
|
|
|
|
def add_lvs_correspondence_points(self):
|
|
"""
|
|
This adds some points for easier debugging if LVS goes wrong.
|
|
These should probably be turned off by default though, since extraction
|
|
will show these as ports in the extracted netlist.
|
|
"""
|
|
|
|
for n in self.control_logic_outputs[0]:
|
|
pin = self.control_logic_insts[0].get_pin(n)
|
|
self.add_label(text=n,
|
|
layer=pin.layer,
|
|
offset=pin.center())
|
|
|
|
def graph_exclude_data_dff(self):
|
|
"""Removes data dff and wmask dff (if applicable) from search graph. """
|
|
# Data dffs and wmask dffs are only for writing so are not useful for evaluating read delay.
|
|
for inst in self.data_dff_insts:
|
|
self.graph_inst_exclude.add(inst)
|
|
if self.write_size:
|
|
for inst in self.wmask_dff_insts:
|
|
self.graph_inst_exclude.add(inst)
|
|
|
|
def graph_exclude_addr_dff(self):
|
|
"""Removes data dff from search graph. """
|
|
# Address is considered not part of the critical path, subjectively removed
|
|
for inst in self.row_addr_dff_insts:
|
|
self.graph_inst_exclude.add(inst)
|
|
|
|
if self.col_addr_dff:
|
|
for inst in self.col_addr_dff_insts:
|
|
self.graph_inst_exclude.add(inst)
|
|
|
|
def graph_exclude_ctrl_dffs(self):
|
|
"""Exclude dffs for CSB, WEB, etc from graph"""
|
|
# Insts located in control logic, exclusion function called here
|
|
for inst in self.control_logic_insts:
|
|
inst.mod.graph_exclude_dffs()
|
|
|
|
def get_sen_name(self, sram_name, port=0):
|
|
"""Returns the s_en spice name."""
|
|
# Naming scheme is hardcoded using this function, should be built into the
|
|
# graph in someway.
|
|
sen_name = "s_en{}".format(port)
|
|
control_conns = self.get_conns(self.control_logic_insts[port])
|
|
# Sanity checks
|
|
if sen_name not in control_conns:
|
|
debug.error("Signal={} not contained in control logic connections={}".format(sen_name,
|
|
control_conns))
|
|
if sen_name in self.pins:
|
|
debug.error("Internal signal={} contained in port list. Name defined by the parent.".format(sen_name))
|
|
return "X{}.{}".format(sram_name, sen_name)
|
|
|
|
def get_cell_name(self, inst_name, row, col):
|
|
"""Gets the spice name of the target bitcell."""
|
|
# Sanity check in case it was forgotten
|
|
if inst_name.find('x') != 0:
|
|
inst_name = 'x' + inst_name
|
|
return self.bank_inst.mod.get_cell_name(inst_name + '.x' + self.bank_inst.name, row, col)
|