mirror of https://github.com/VLSIDA/OpenRAM.git
9749c522d1
this is the first step to allow engineers, porting technologies, more room for routing their handmade cells. For now, we don't allow the specification of power_grids where the lower layer prefers to be routed vertically. This is due to the router not connecting some pins properly in that case. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> |
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| .. | ||
| tests | ||
| direction.py | ||
| grid.py | ||
| grid_cell.py | ||
| grid_path.py | ||
| grid_utils.py | ||
| pin_group.py | ||
| router.py | ||
| router_tech.py | ||
| signal_grid.py | ||
| signal_router.py | ||
| supply_grid.py | ||
| supply_grid_router.py | ||
| supply_tree_router.py | ||
| vector3d.py | ||