mirror of https://github.com/VLSIDA/OpenRAM.git
159 lines
5.2 KiB
Python
159 lines
5.2 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California
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# All rights reserved.
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#
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import sys
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from tech import drc, parameter
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from math import log, ceil
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import debug
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import design
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from sram_factory import factory
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from vector import vector
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from globals import OPTS
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class port_address(design.design):
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"""
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Create the address port (row decoder and wordline driver)..
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"""
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def __init__(self, cols, rows, name=""):
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self.num_cols = cols
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self.num_rows = rows
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self.addr_size = ceil(log(self.num_rows, 2))
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if name == "":
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name = "port_address_{0}_{1}".format(cols,rows)
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design.design.__init__(self, name)
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debug.info(2, "create data port of cols {0} rows {1}".format(cols,rows))
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self.create_netlist()
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if not OPTS.netlist_only:
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debug.check(len(self.all_ports)<=2,"Bank layout cannot handle more than two ports.")
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self.create_layout()
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self.add_boundary()
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def create_netlist(self):
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self.add_pins()
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self.add_modules()
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self.create_row_decoder()
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self.create_wordline_driver()
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def create_layout(self):
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self.place_instances()
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self.route_layout()
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self.DRC_LVS()
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def add_pins(self):
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""" Adding pins for port address module"""
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for bit in range(self.addr_size):
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self.add_pin("addr_{0}".format(bit),"INPUT")
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self.add_pin("wl_en", "INPUT")
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for bit in range(self.num_rows):
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self.add_pin("wl_{0}".format(bit),"OUTPUT")
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self.add_pin("vdd","POWER")
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self.add_pin("gnd","GROUND")
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def route_layout(self):
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""" Create routing amoung the modules """
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self.route_pins()
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self.route_internal()
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self.route_supplies()
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def route_supplies(self):
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""" Propagate all vdd/gnd pins up to this level for all modules """
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for inst in self.insts:
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self.copy_power_pins(inst,"vdd")
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self.copy_power_pins(inst,"gnd")
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def route_pins(self):
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for row in range(self.addr_size):
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decoder_name = "addr_{}".format(row)
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self.copy_layout_pin(self.row_decoder_inst, decoder_name)
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for row in range(self.num_rows):
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driver_name = "wl_{}".format(row)
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self.copy_layout_pin(self.wordline_driver_inst, driver_name)
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self.copy_layout_pin(self.wordline_driver_inst, "en", "wl_en")
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def route_internal(self):
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for row in range(self.num_rows):
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# The pre/post is to access the pin from "outside" the cell to avoid DRCs
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decoder_out_pos = self.row_decoder_inst.get_pin("decode_{}".format(row)).rc()
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driver_in_pos = self.wordline_driver_inst.get_pin("in_{}".format(row)).lc()
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mid1 = decoder_out_pos.scale(0.5, 1) + driver_in_pos.scale(0.5, 0)
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mid2 = decoder_out_pos.scale(0.5, 0) + driver_in_pos.scale(0.5, 1)
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self.add_path("m1", [decoder_out_pos, mid1, mid2, driver_in_pos])
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def add_modules(self):
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self.row_decoder = factory.create(module_type="decoder",
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num_outputs=self.num_rows)
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self.add_mod(self.row_decoder)
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self.wordline_driver = factory.create(module_type="wordline_driver",
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rows=self.num_rows,
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cols=self.num_cols)
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self.add_mod(self.wordline_driver)
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def create_row_decoder(self):
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""" Create the hierarchical row decoder """
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self.row_decoder_inst = self.add_inst(name="row_decoder",
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mod=self.row_decoder)
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temp = []
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for bit in range(self.addr_size):
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temp.append("addr_{0}".format(bit))
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for row in range(self.num_rows):
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temp.append("dec_out_{0}".format(row))
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temp.extend(["vdd", "gnd"])
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self.connect_inst(temp)
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def create_wordline_driver(self):
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""" Create the Wordline Driver """
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self.wordline_driver_inst = self.add_inst(name="wordline_driver",
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mod=self.wordline_driver)
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temp = []
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for row in range(self.num_rows):
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temp.append("dec_out_{0}".format(row))
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for row in range(self.num_rows):
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temp.append("wl_{0}".format(row))
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temp.append("wl_en")
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temp.append("vdd")
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temp.append("gnd")
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self.connect_inst(temp)
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def place_instances(self):
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"""
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Compute the offsets and place the instances.
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"""
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# A space for wells or jogging m2
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self.m2_gap = max(2*drc("pwell_to_nwell") + drc("nwell_enclose_active"),
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3*self.m2_pitch)
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row_decoder_offset = vector(0,0)
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wordline_driver_offset = vector(self.row_decoder.width + self.m2_gap,0)
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self.wordline_driver_inst.place(wordline_driver_offset)
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self.row_decoder_inst.place(row_decoder_offset)
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self.height = self.row_decoder.height
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self.width = self.wordline_driver_inst.rx()
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