mirror of https://github.com/VLSIDA/OpenRAM.git
129 lines
4.4 KiB
Python
129 lines
4.4 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from base import design
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import debug
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from base import vector
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from sram_factory import factory
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from globals import OPTS
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class precharge_array(design):
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"""
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Dynamically generated precharge array of all bitlines. Cols is number
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of bit line columns, height is the height of the bit-cell array.
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"""
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def __init__(self, name, columns, offsets=None, size=1, bitcell_bl="bl", bitcell_br="br", column_offset=0):
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super().__init__(name)
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debug.info(1, "Creating {0}".format(self.name))
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self.add_comment("cols: {0} size: {1} bl: {2} br: {3}".format(columns, size, bitcell_bl, bitcell_br))
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self.columns = columns
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self.offsets = offsets
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self.size = size
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self.bitcell_bl = bitcell_bl
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self.bitcell_br = bitcell_br
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self.column_offset = column_offset
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if OPTS.tech_name == "sky130":
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self.en_bar_layer = "m3"
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else:
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self.en_bar_layer = "m1"
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def get_bl_name(self):
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bl_name = self.pc_cell.get_bl_names()
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return bl_name
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def get_br_name(self):
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br_name = self.pc_cell.get_br_names()
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return br_name
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def add_pins(self):
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"""Adds pins for spice file"""
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for i in range(self.columns):
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# These are outputs from the precharge only
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self.add_pin("bl_{0}".format(i), "OUTPUT")
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self.add_pin("br_{0}".format(i), "OUTPUT")
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self.add_pin("en_bar", "INPUT")
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self.add_pin("vdd", "POWER")
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def create_netlist(self):
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self.add_modules()
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self.add_pins()
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self.create_insts()
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def create_layout(self):
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self.place_insts()
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self.width = self.offsets[-1] + self.pc_cell.width
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self.height = self.pc_cell.height
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self.add_layout_pins()
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self.route_supplies()
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self.add_boundary()
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self.DRC_LVS()
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def add_modules(self):
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self.pc_cell = factory.create(module_type=OPTS.precharge,
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size=self.size,
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bitcell_bl=self.bitcell_bl,
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bitcell_br=self.bitcell_br)
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self.cell = factory.create(module_type=OPTS.bitcell)
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def add_layout_pins(self):
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en_pin = self.pc_cell.get_pin("en_bar")
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self.route_horizontal_pins("en_bar", layer=self.en_bar_layer)
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for inst in self.local_insts:
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self.add_via_stack_center(from_layer=en_pin.layer,
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to_layer=self.en_bar_layer,
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offset=inst.get_pin("en_bar").center())
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for i in range(len(self.local_insts)):
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inst = self.local_insts[i]
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self.copy_layout_pin(inst, "bl", "bl_{0}".format(i))
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self.copy_layout_pin(inst, "br", "br_{0}".format(i))
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def route_supplies(self):
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self.route_horizontal_pins("vdd")
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def create_insts(self):
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"""Creates a precharge array by horizontally tiling the precharge cell"""
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self.local_insts = []
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for i in range(self.columns):
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name = "pre_column_{0}".format(i)
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offset = vector(self.pc_cell.width * i, 0)
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inst = self.add_inst(name=name,
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mod=self.pc_cell,
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offset=offset)
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self.local_insts.append(inst)
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self.connect_inst(["bl_{0}".format(i), "br_{0}".format(i), "en_bar", "vdd"])
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def place_insts(self):
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""" Places precharge array by horizontally tiling the precharge cell"""
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# Default to single spaced columns
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if not self.offsets:
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self.offsets = [n * self.pc_cell.width for n in range(self.columns)]
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for i, xoffset in enumerate(self.offsets):
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if self.cell.mirror.y and (i + self.column_offset) % 2:
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mirror = "MY"
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tempx = xoffset + self.pc_cell.width
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else:
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mirror = ""
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tempx = xoffset
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offset = vector(tempx, 0)
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self.local_insts[i].place(offset=offset, mirror=mirror)
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