OpenRAM/compiler/base
mrg fc12ea24e9 Add boundary to every module and pgate for visual debug. 2019-06-03 15:27:37 -07:00
..
contact.py Add back scn3me_subm support 2019-06-03 15:27:37 -07:00
design.py Pbitcell updates. 2019-06-03 15:27:37 -07:00
geometry.py Update copyright to correct years. 2019-05-06 06:50:15 -07:00
hierarchy_design.py Update copyright to correct years. 2019-05-06 06:50:15 -07:00
hierarchy_layout.py Add boundary to every module and pgate for visual debug. 2019-06-03 15:27:37 -07:00
hierarchy_spice.py Update copyright to correct years. 2019-05-06 06:50:15 -07:00
lef.py Update copyright to correct years. 2019-05-06 06:50:15 -07:00
pin_layout.py Update copyright to correct years. 2019-05-06 06:50:15 -07:00
route.py Update copyright to correct years. 2019-05-06 06:50:15 -07:00
utils.py Update copyright to correct years. 2019-05-06 06:50:15 -07:00
vector.py Update copyright to correct years. 2019-05-06 06:50:15 -07:00
verilog.py Update copyright to correct years. 2019-05-06 06:50:15 -07:00
wire.py Update copyright to correct years. 2019-05-06 06:50:15 -07:00
wire_path.py Update copyright to correct years. 2019-05-06 06:50:15 -07:00