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OpenRAM/compiler/bitcells
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mrg 4a67f7dc71 Thin-cell decoder changes. 
Add hard decoder gates (nand, inv, pnan)
Add conditions for routing using LI layer in s8.
Generalize bus layers for decoders.
Move custom cells to own directory.
Fixed via directions, etc.
Add 4x16 hierarchical decoder and test case
 		2020-05-29 10:36:07 -07:00
..
bitcell.py Thin-cell decoder changes. 2020-05-29 10:36:07 -07:00
bitcell_1rw_1r.py bitcell: Remove hardcoded signal pins 2020-02-12 15:37:51 +01:00
bitcell_1w_1r.py bitcell: Remove hardcoded signal pins 2020-02-12 15:37:51 +01:00
bitcell_base.py Refactor bitcell to bitcell_base. Pep8 format bitcells. 2019-10-06 01:08:23 +00:00
dummy_bitcell.py bitcell: Remove hardcoded signal pins 2020-02-12 15:37:51 +01:00
dummy_bitcell_1rw_1r.py bitcell: Remove hardcoded signal pins 2020-02-12 15:37:51 +01:00
dummy_bitcell_1w_1r.py bitcell: Remove hardcoded signal pins 2020-02-12 15:37:51 +01:00
dummy_pbitcell.py Add bbox for special DRC rule boundary 2019-12-05 23:14:25 +00:00
pbitcell.py Changes to simplify metal preferred directions and pitches. 2020-05-10 11:32:45 -07:00
replica_bitcell.py bitcell: Remove hardcoded signal pins 2020-02-12 15:37:51 +01:00
replica_bitcell_1rw_1r.py bitcell: Remove hardcoded signal pins 2020-02-12 15:37:51 +01:00
replica_bitcell_1w_1r.py bitcell: Remove hardcoded signal pins 2020-02-12 15:37:51 +01:00
replica_pbitcell.py Add bbox for special DRC rule boundary 2019-12-05 23:14:25 +00:00