mirror of https://github.com/VLSIDA/OpenRAM.git
222 lines
9.1 KiB
Python
222 lines
9.1 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import bitcell_base_array
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from globals import OPTS
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from sram_factory import factory
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from vector import vector
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import debug
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class local_bitcell_array(bitcell_base_array.bitcell_base_array):
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"""
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A local bitcell array is a bitcell array with a wordline driver.
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This can either be a single aray on its own if there is no hierarchical WL
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or it can be combined into a larger array with hierarchical WL.
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"""
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def __init__(self, rows, cols, rbl, add_rbl=None, name=""):
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super().__init__(name, rows, cols, 0)
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debug.info(2, "create local array of size {} rows x {} cols words".format(rows, cols))
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self.rows = rows
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self.cols = cols
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self.rbl = rbl
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if add_rbl == None:
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self.add_rbl = rbl
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else:
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self.add_rbl = add_rbl
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debug.check(len(self.all_ports) < 3, "Local bitcell array only supports dual port or less.")
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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# We don't offset this because we need to align
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# the replica bitcell in the control logic
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# self.offset_all_coordinates()
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def create_netlist(self):
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""" Create and connect the netlist """
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self.add_modules()
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self.add_pins()
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self.create_instances()
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def create_layout(self):
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self.place()
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self.add_layout_pins()
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self.route()
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self.add_boundary()
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self.DRC_LVS()
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def add_modules(self):
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""" Add the modules used in this design """
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# This is just used for names
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self.cell = factory.create(module_type="bitcell")
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self.bitcell_array = factory.create(module_type="replica_bitcell_array",
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cols=self.cols,
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rows=self.rows,
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rbl=self.rbl,
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add_rbl=self.add_rbl)
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self.add_mod(self.bitcell_array)
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self.wl_array = factory.create(module_type="wordline_buffer_array",
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rows=self.rows + 1,
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cols=self.cols)
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self.add_mod(self.wl_array)
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def add_pins(self):
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self.wordline_names = []
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self.driver_wordline_outputs = []
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self.array_wordline_inputs = []
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# Port 0
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wordline_inputs = [x for x in self.bitcell_array.get_wordline_names(0) if not x.startswith("dummy")]
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if len(self.all_ports) > 1:
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# Drop off the RBL for port 1
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self.wordline_names.append(wordline_inputs[:-1])
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else:
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self.wordline_names.append(wordline_inputs)
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self.driver_wordline_outputs.append([x + "i" for x in self.wordline_names[-1]])
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self.array_wordline_inputs.append([x + "i" if not x.startswith("dummy") else "gnd" for x in self.bitcell_array.get_wordline_names(0)])
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# Port 1
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if len(self.all_ports) > 1:
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self.wordline_names.append([x for x in self.bitcell_array.get_wordline_names(1) if not x.startswith("dummy")][1:])
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self.driver_wordline_outputs.append([x + "i" for x in self.wordline_names[-1]])
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self.array_wordline_inputs.append([x + "i" if not x.startswith("dummy") else "gnd" for x in self.bitcell_array.get_wordline_names(1)])
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self.all_driver_wordline_inputs = [x for x in self.bitcell_array.get_wordline_names() if not x.startswith("dummy")]
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self.replica_names = self.bitcell_array.get_rbl_wordline_names()
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self.gnd_wl_names = []
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# Connect unused RBL WL to gnd
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array_rbl_names = set([x for x in self.bitcell_array.get_all_wordline_names() if x.startswith("rbl")])
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dummy_rbl_names = set([x for x in self.bitcell_array.get_all_wordline_names() if x.startswith("dummy")])
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rbl_wl_names = set([x for port in self.all_ports for x in self.bitcell_array.get_rbl_wordline_names(port)])
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self.gnd_wl_names = list((array_rbl_names - rbl_wl_names) | dummy_rbl_names)
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self.all_array_wordline_inputs = [x + "i" if x not in self.gnd_wl_names else "gnd" for x in self.bitcell_array.get_wordline_names()]
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self.bitline_names = self.bitcell_array.bitline_names
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# Arrays are always:
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# word lines (bottom to top)
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# bit lines (left to right)
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# vdd
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# gnd
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for port in self.all_ports:
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self.add_pin_list(self.wordline_names[port], "INPUT")
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for port in self.all_ports:
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self.add_pin_list(self.bitline_names[port], "INOUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def create_instances(self):
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""" Create the module instances used in this design """
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self.wl_insts = []
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for port in self.all_ports:
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self.wl_insts.append(self.add_inst(name="wl_driver",
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mod=self.wl_array))
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self.connect_inst(self.wordline_names[port] + self.driver_wordline_outputs[port] + ["vdd", "gnd"])
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self.bitcell_array_inst = self.add_inst(name="array",
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mod=self.bitcell_array)
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self.connect_inst(self.all_array_wordline_inputs + self.bitline_names + ["vdd", "gnd"])
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def place(self):
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""" Place the bitcelll array to the right of the wl driver. """
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# FIXME: Replace this with a tech specific paramter
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driver_to_array_spacing = 3 * self.m3_pitch
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self.wl_insts[0].place(vector(0, self.cell.height))
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self.bitcell_array_inst.place(vector(self.wl_insts[0].rx() + driver_to_array_spacing,
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0))
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if len(self.all_ports) > 1:
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self.wl_insts[1].place(vector(self.bitcell_array_inst.rx() + self.wl_array.width + driver_to_array_spacing,
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2 * self.cell.height),
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mirror="MY")
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self.height = self.bitcell_array.height
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self.width = self.bitcell_array_inst.rx()
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def route_unused_wordlines(self):
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""" Connect the unused RBL and dummy wordlines to gnd """
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for wl_name in self.gnd_wl_names:
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pin = self.bitcell_array_inst.get_pin(wl_name)
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pin_layer = pin.layer
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layer_pitch = 1.5 * getattr(self, "{}_pitch".format(pin_layer))
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left_pin_loc = pin.lc()
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right_pin_loc = pin.rc()
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# Place the pins a track outside of the array
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left_loc = left_pin_loc - vector(layer_pitch, 0)
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right_loc = right_pin_loc + vector(layer_pitch, 0)
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self.add_power_pin("gnd", left_loc, directions=("H", "H"))
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self.add_power_pin("gnd", right_loc, directions=("H", "H"))
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# Add a path to connect to the array
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self.add_path(pin_layer, [left_loc, left_pin_loc])
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self.add_path(pin_layer, [right_loc, right_pin_loc])
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def add_layout_pins(self):
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for (x, y) in zip(self.bitline_names, self.bitcell_array.get_inouts()):
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self.copy_layout_pin(self.bitcell_array_inst, y, x)
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for port in self.all_ports:
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for (x, y) in zip(self.wordline_names[port], self.wl_array.get_inputs()):
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self.copy_layout_pin(self.wl_insts[port], y, x)
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supply_insts = [*self.wl_insts, self.bitcell_array_inst]
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for pin_name in ["vdd", "gnd"]:
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for inst in supply_insts:
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pin_list = inst.get_pins(pin_name)
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for pin in pin_list:
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self.add_power_pin(name=pin_name,
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loc=pin.center(),
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start_layer=pin.layer)
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def route(self):
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for port in self.all_ports:
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if port == 0:
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array_names = [x for x in self.bitcell_array.get_wordline_names(port) if not x.startswith("dummy")]
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if len(self.all_ports) > 1:
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# Drop off the RBL for port 1
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array_names = array_names[:-1]
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else:
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array_names = [x for x in self.bitcell_array.get_wordline_names(port) if not x.startswith("dummy")][1:]
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for (driver_name, array_name) in zip(self.wl_array.get_outputs(), array_names):
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out_pin = self.wl_insts[port].get_pin(driver_name)
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in_pin = self.bitcell_array_inst.get_pin(array_name)
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if port == 0:
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out_loc = out_pin.rc()
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mid_loc = vector(self.wl_insts[port].rx() + 1.5 * self.m3_pitch, out_loc.y)
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in_loc = in_pin.lc()
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else:
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out_loc = out_pin.lc()
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mid_loc = vector(self.wl_insts[port].lx() - 1.5 * self.m3_pitch, out_loc.y)
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in_loc = in_pin.rc()
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self.add_path(out_pin.layer, [out_loc, mid_loc, in_loc])
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self.route_unused_wordlines()
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