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OpenRAM/compiler/tests
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Matt Guthaus 29c5ab48f0 Add spice pruning for speed-up. Fix spice search bugs. Add time in stages to openram output. 2017-11-14 13:24:14 -08:00
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golden Fix bug in multifinger ptx. Replace LEF file with new snapped layout. 2017-10-06 16:23:23 -07:00
00_code_format_check_test.py Fixed format errors 2017-04-24 13:50:19 -07:00
01_library_drc_test.py Merge use-temp-dir-pid 2016-11-12 08:55:42 -08:00
02_library_lvs_test.py Merge use-temp-dir-pid 2016-11-12 08:55:42 -08:00
03_contact_test.py Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
03_path_test.py Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
03_ptx_1finger_nmos_test.py Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
03_ptx_1finger_pmos_test.py Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
03_ptx_3finger_nmos_test.py Added pins to the ptx class. Modified pin class to do lazy write of GDS shapes to allow removal of pins. 2017-10-05 17:35:05 -07:00
03_ptx_3finger_pmos_test.py Added pins to the ptx class. Modified pin class to do lazy write of GDS shapes to allow removal of pins. 2017-10-05 17:35:05 -07:00
03_wire_test.py Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
04_nand_2_test.py Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
04_nand_3_test.py Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
04_nor_2_test.py Two bank SRAMs working in both technologies. 2017-09-29 16:22:13 -07:00
04_pinv_test.py Fix bug in multifinger ptx. Replace LEF file with new snapped layout. 2017-10-06 16:23:23 -07:00
04_precharge_test.py Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
04_wordline_driver_test.py Fix new offset snap problems in wordline drive. Fix ptx multifinger pin bug. Add new add_center_rect function. 2017-10-06 15:30:15 -07:00
05_bitcell_array_test.py Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
06_hierarchical_decoder_test.py Fixed several LVS errors. Bank passes LVS for 2-way and 4-way, but not 1-way or 8-way. 2017-08-24 16:22:14 -07:00
06_hierarchical_predecode2x4_test.py Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
06_hierarchical_predecode3x8_test.py Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
07_single_level_column_mux_array_test.py Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
08_precharge_array_test.py Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
09_sense_amp_array_test.py Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
10_write_driver_array_test.py Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
11_ms_flop_array_test.py Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
12_tri_gate_array_test.py Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
13_replica_bitline_test.py Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
14_delay_chain_test.py Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
16_control_logic_test.py Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
19_multi_bank_test.py Two bank SRAMs working in both technologies. 2017-09-29 16:22:13 -07:00
19_single_bank_test.py Two bank SRAMs working in both technologies. 2017-09-29 16:22:13 -07:00
20_sram_1bank_test.py Two bank SRAMs working in both technologies. 2017-09-29 16:22:13 -07:00
20_sram_2bank_test.py Two bank SRAMs working in both technologies. 2017-09-29 16:22:13 -07:00
20_sram_4bank_test.py 4-bank SRAMs are now working. 2017-10-04 18:05:45 -07:00
21_hspice_delay_test.py Add customsim (xa) as optional simulator. Fix regex to support scientific notation. Go through list of preferred simulators in order. Always abort if command-line simulator not found. 2017-11-12 10:42:41 -08:00
21_hspice_setuphold_test.py Add customsim (xa) as optional simulator. Fix regex to support scientific notation. Go through list of preferred simulators in order. Always abort if command-line simulator not found. 2017-11-12 10:42:41 -08:00
21_ngspice_delay_test.py Add customsim (xa) as optional simulator. Fix regex to support scientific notation. Go through list of preferred simulators in order. Always abort if command-line simulator not found. 2017-11-12 10:42:41 -08:00
21_ngspice_setuphold_test.py Add customsim (xa) as optional simulator. Fix regex to support scientific notation. Go through list of preferred simulators in order. Always abort if command-line simulator not found. 2017-11-12 10:42:41 -08:00
22_pex_func_test_with_pinv.py Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity. 2017-06-02 11:11:57 -07:00
22_sram_func_test.py Change default delay modeling to analytical. Add command-line option characterization by simulation (-c). 2017-11-09 11:13:44 -08:00
23_lib_sram_model_test.py Fix lib test to enable spice simulation. Fixed bug with change in default argument. 2017-06-05 09:07:52 -07:00
23_lib_sram_prune_test.py Add spice pruning for speed-up. Fix spice search bugs. Add time in stages to openram output. 2017-11-14 13:24:14 -08:00
23_lib_sram_test.py Add spice pruning for speed-up. Fix spice search bugs. Add time in stages to openram output. 2017-11-14 13:24:14 -08:00
24_lef_sram_test.py Moved output of tests 23-25 to openram_temp 2016-11-12 11:15:34 -08:00
25_verilog_sram_test.py Moved output of tests 23-25 to openram_temp 2016-11-12 11:15:34 -08:00
30_openram_test.py Moved output of tests 30 to openram_temp 2016-11-12 11:15:55 -08:00
README RELEASE 1.0 2016-11-08 09:57:35 -08:00
config_20_freepdk45.py Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
config_20_scn3me_subm.py Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
regress.py Change some debug levels. Fix ngspice test values. ix cwd warning in some tests. 2016-11-15 08:57:06 -08:00
testutils.py Improved characterizer. 2017-07-06 08:42:25 -07:00

README 

Note that the tests turn off DRC/LVS when they perform their own check
for performance improvement. However, it must be turned back on before
the test runs an assert.