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luke
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OpenRAM
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https://github.com/VLSIDA/OpenRAM.git
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3ffcad0db8876d974b26fe77d68989209bf4eb1a
OpenRAM
/
technology
/
scn4m_subm
T
History
Matt Guthaus
3ffcad0db8
Add port makeall for removing symmetry problems in netgen
2019-04-26 09:17:52 -07:00
..
gds_lib
Copy 1rw/1r cell to 1w/1r.
2019-02-24 09:54:45 -08:00
mag_lib
Add port makeall for removing symmetry problems in netgen
2019-04-26 09:17:52 -07:00
models
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
sp_lib
Copy 1rw/1r cell to 1w/1r.
2019-02-24 09:54:45 -08:00
sue_lib
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
tech
Added more accurate bitline delay capacitance estimations
2019-04-09 01:56:32 -07:00
tf
Remove file named LICENSE since it is in the README for the tech files
2019-01-25 15:58:49 -08:00
__init__.py
Simplify tech organization and import
2019-03-06 07:41:38 -08:00
