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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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3ffcad0db8876d974b26fe77d68989209bf4eb1a
OpenRAM/compiler/verify
T
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Matt Guthaus 3ffcad0db8 Add port makeall for removing symmetry problems in netgen
2019-04-26 09:17:52 -07:00
..
__init__.py
Add none option for verify wrapper with warning messages.
2018-09-11 10:17:24 -07:00
assura.py
Fix arguments for none verification
2019-02-24 10:49:35 -08:00
calibre.py
Create auxiliary run_drc.sh and run_lvs.sh with arguments for calibre
2019-04-22 15:12:59 -07:00
magic.py
Add port makeall for removing symmetry problems in netgen
2019-04-26 09:17:52 -07:00
none.py
Fix arguments for none verification
2019-02-24 10:49:35 -08:00
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