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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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3d2abc08730bf0c6b7a3c8c8bd3ebd64abd12c52
OpenRAM/technology/freepdk45/sp_lib
T
History
Matt Guthaus c01f0f5274 Merge branch 'dev' into fix_rbl_cell_connections
2018-11-05 16:38:46 -08:00
..
cell_1rw_1r.sp
Added custom 1rw+1r bitcell. Testing are currently failing.
2018-10-22 17:02:21 -07:00
cell_6t.sp
Comment spice cells. Change replica to short Q to vdd instead of Qbar to gnd.
2018-11-05 10:59:08 -08:00
dff.sp
Add dff_buf for buffered flop arrays.
2018-03-04 16:13:10 -08:00
replica_cell_1rw_1r.sp
Fixed error in control logic test. Added gds/sp for replica cell 1rw+1r.
2018-10-31 00:06:34 -07:00
replica_cell_6t.sp
Modify replica cell spice in FreePDK45 to short Qbar to vdd
2018-11-05 11:42:42 -08:00
sense_amp.sp
Fix pin nameon sense amp spice. Fix NAND2 bug in hierarchical decoder.
2018-02-02 14:08:56 -08:00
tri_gate.sp
RELEASE 1.0
2016-11-08 09:57:35 -08:00
write_driver.sp
Change wen to en in spice lib files. Check lvs report insted of stdout with netgen.
2018-02-01 05:38:48 -08:00
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