This website requires JavaScript.
Explore
Help
Sign In
luke
/
OpenRAM
Watch
1
Star
0
Fork
0
mirror of
https://github.com/VLSIDA/OpenRAM.git
synced
2026-08-29 09:30:38 +02:00
Code
Issues
Packages
Projects
Releases
Wiki
Activity
Files
3d2abc08730bf0c6b7a3c8c8bd3ebd64abd12c52
OpenRAM
/
compiler
/
bitcells
T
History
Matt Guthaus
1fe767343e
Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.
2018-11-07 11:31:44 -08:00
..
bitcell_1rw_1r.py
Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.
2018-11-07 11:31:44 -08:00
bitcell.py
Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.
2018-11-07 11:31:44 -08:00
pbitcell.py
Changed the analytical delay model to accept multiport options. Little substance to the values generated.
2018-10-26 00:08:13 -07:00
replica_bitcell_1rw_1r.py
Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.
2018-11-07 11:31:44 -08:00
replica_bitcell.py
Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.
2018-11-07 11:31:44 -08:00
replica_pbitcell.py
Move replica bitcells to new bitcells subdir
2018-10-24 09:06:29 -07:00