mirror of https://github.com/VLSIDA/OpenRAM.git
629 lines
24 KiB
Python
629 lines
24 KiB
Python
from tech import drc
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import debug
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import design
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from math import log
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from math import sqrt
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import math
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import contact
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from pnand2 import pnand2
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from pnand3 import pnand3
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from pinv import pinv
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from hierarchical_predecode2x4 import hierarchical_predecode2x4 as pre2x4
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from hierarchical_predecode3x8 import hierarchical_predecode3x8 as pre3x8
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from vector import vector
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from globals import OPTS
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class hierarchical_decoder(design.design):
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"""
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Dynamically generated hierarchical decoder.
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"""
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def __init__(self, rows):
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design.design.__init__(self, "hierarchical_decoder_{0}rows".format(rows))
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from importlib import reload
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c = reload(__import__(OPTS.bitcell))
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self.mod_bitcell = getattr(c, OPTS.bitcell)
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b = self.mod_bitcell()
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self.bitcell_height = b.height
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self.NAND_FORMAT = "DEC_NAND_{0}"
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self.INV_FORMAT = "DEC_INV_{0}"
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self.pre2x4_inst = []
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self.pre3x8_inst = []
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self.rows = rows
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self.num_inputs = int(math.log(self.rows, 2))
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(self.no_of_pre2x4,self.no_of_pre3x8)=self.determine_predecodes(self.num_inputs)
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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self.add_modules()
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self.setup_netlist_constants()
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self.add_pins()
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self.create_pre_decoder()
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self.create_row_decoder()
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def create_layout(self):
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self.setup_layout_constants()
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self.place_pre_decoder()
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self.place_row_decoder()
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self.route_input_rails()
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self.route_predecode_rails()
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self.route_vdd_gnd()
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self.offset_all_coordinates()
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self.DRC_LVS()
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def add_modules(self):
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self.inv = pinv()
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self.add_mod(self.inv)
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self.nand2 = pnand2()
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self.add_mod(self.nand2)
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self.nand3 = pnand3()
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self.add_mod(self.nand3)
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self.add_decoders()
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def add_decoders(self):
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""" Create the decoders based on the number of pre-decodes """
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self.pre2_4 = pre2x4()
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self.add_mod(self.pre2_4)
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self.pre3_8 = pre3x8()
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self.add_mod(self.pre3_8)
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def determine_predecodes(self,num_inputs):
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""" Determines the number of 2:4 pre-decoder and 3:8 pre-decoder
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needed based on the number of inputs """
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if (num_inputs == 2):
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return (1,0)
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elif (num_inputs == 3):
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return(0,1)
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elif (num_inputs == 4):
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return(2,0)
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elif (num_inputs == 5):
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return(1,1)
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elif (num_inputs == 6):
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return(3,0)
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elif (num_inputs == 7):
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return(2,1)
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elif (num_inputs == 8):
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return(1,2)
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elif (num_inputs == 9):
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return(0,3)
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else:
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debug.error("Invalid number of inputs for hierarchical decoder",-1)
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def setup_netlist_constants(self):
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self.predec_groups = [] # This array is a 2D array.
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# Distributing vertical rails to different groups. One group belongs to one pre-decoder.
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# For example, for two 2:4 pre-decoder and one 3:8 pre-decoder, we will
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# have total 16 output lines out of these 3 pre-decoders and they will
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# be distributed as [ [0,1,2,3] ,[4,5,6,7], [8,9,10,11,12,13,14,15] ]
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# in self.predec_groups
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index = 0
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for i in range(self.no_of_pre2x4):
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lines = []
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for j in range(4):
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lines.append(index)
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index = index + 1
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self.predec_groups.append(lines)
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for i in range(self.no_of_pre3x8):
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lines = []
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for j in range(8):
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lines.append(index)
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index = index + 1
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self.predec_groups.append(lines)
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def setup_layout_constants(self):
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""" Calculate the overall dimensions of the hierarchical decoder """
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# If we have 4 or fewer rows, the predecoder is the decoder itself
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if self.num_inputs>=4:
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self.total_number_of_predecoder_outputs = 4*self.no_of_pre2x4 + 8*self.no_of_pre3x8
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else:
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self.total_number_of_predecoder_outputs = 0
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debug.error("Not enough rows ({}) for a hierarchical decoder. Non-hierarchical not supported yet.".format(self.num_inputs),-1)
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# Calculates height and width of pre-decoder,
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if self.no_of_pre3x8 > 0:
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self.predecoder_width = self.pre3_8.width
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else:
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self.predecoder_width = self.pre2_4.width
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self.predecoder_height = self.pre2_4.height*self.no_of_pre2x4 + self.pre3_8.height*self.no_of_pre3x8
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# Calculates height and width of row-decoder
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if (self.num_inputs == 4 or self.num_inputs == 5):
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nand_width = self.nand2.width
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else:
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nand_width = self.nand3.width
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self.internal_routing_width = self.m2_pitch*self.total_number_of_predecoder_outputs
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self.row_decoder_height = self.inv.height * self.rows
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self.input_routing_width = (self.num_inputs+1) * self.m2_pitch
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# Calculates height and width of hierarchical decoder
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self.height = self.row_decoder_height
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self.width = self.input_routing_width + self.predecoder_width \
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+ self.internal_routing_width + nand_width + self.inv.width
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def route_input_rails(self):
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""" Create input rails for the predecoders """
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# inputs should be as high as the decoders
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input_height = self.no_of_pre2x4*self.pre2_4.height + self.no_of_pre3x8*self.pre3_8.height
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# Find the left-most predecoder
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min_x = 0
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if self.no_of_pre2x4 > 0:
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min_x = min(min_x, -self.pre2_4.width)
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if self.no_of_pre3x8 > 0:
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min_x = min(min_x, -self.pre3_8.width)
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input_offset=vector(min_x - self.input_routing_width,0)
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input_bus_names = ["addr_{0}".format(i) for i in range(self.num_inputs)]
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self.input_rails = self.create_vertical_pin_bus(layer="metal2",
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pitch=self.m2_pitch,
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offset=input_offset,
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names=input_bus_names,
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length=input_height)
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self.route_input_to_predecodes()
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def route_input_to_predecodes(self):
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""" Route the vertical input rail to the predecoders """
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for pre_num in range(self.no_of_pre2x4):
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for i in range(2):
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index = pre_num * 2 + i
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input_pos = self.input_rails["addr_{}".format(index)]
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in_name = "in_{}".format(i)
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decoder_pin = self.pre2x4_inst[pre_num].get_pin(in_name)
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# To prevent conflicts, we will offset each input connect so
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# that it aligns with the vdd/gnd rails
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decoder_offset = decoder_pin.bc() + vector(0,(i+1)*self.inv.height)
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input_offset = input_pos.scale(1,0) + decoder_offset.scale(0,1)
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self.route_input_rail(decoder_offset, input_offset)
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for pre_num in range(self.no_of_pre3x8):
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for i in range(3):
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index = pre_num * 3 + i + self.no_of_pre2x4 * 2
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input_pos = self.input_rails["addr_{}".format(index)]
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in_name = "in_{}".format(i)
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decoder_pin = self.pre3x8_inst[pre_num].get_pin(in_name)
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# To prevent conflicts, we will offset each input connect so
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# that it aligns with the vdd/gnd rails
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decoder_offset = decoder_pin.bc() + vector(0,(i+1)*self.inv.height)
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input_offset = input_pos.scale(1,0) + decoder_offset.scale(0,1)
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self.route_input_rail(decoder_offset, input_offset)
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def route_input_rail(self, input_offset, output_offset):
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""" Route a vertical M2 coordinate to another vertical M2 coordinate to the predecode inputs """
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self.add_via_center(layers=("metal2", "via2", "metal3"),
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offset=input_offset,
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rotate=90)
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self.add_via_center(layers=("metal2", "via2", "metal3"),
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offset=output_offset,
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rotate=90)
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self.add_path(("metal3"), [input_offset, output_offset])
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def add_pins(self):
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""" Add the module pins """
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for i in range(self.num_inputs):
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self.add_pin("addr_{0}".format(i))
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for j in range(self.rows):
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self.add_pin("decode_{0}".format(j))
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self.add_pin("vdd")
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self.add_pin("gnd")
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def create_pre_decoder(self):
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""" Creates pre-decoder and places labels input address [A] """
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for i in range(self.no_of_pre2x4):
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self.create_pre2x4(i)
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for i in range(self.no_of_pre3x8):
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self.create_pre3x8(i)
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def create_pre2x4(self,num):
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""" Add a 2x4 predecoder to the left of the origin """
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if (self.num_inputs == 2):
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index_off1 = index_off2 = 0
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else:
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index_off1 = num * 2
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index_off2 = num * 4
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pins = []
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for input_index in range(2):
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pins.append("addr_{0}".format(input_index + index_off1))
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for output_index in range(4):
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pins.append("out_{0}".format(output_index + index_off2))
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pins.extend(["vdd", "gnd"])
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self.pre2x4_inst.append(self.add_inst(name="pre_{0}".format(num),
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mod=self.pre2_4))
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self.connect_inst(pins)
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def create_pre3x8(self,num):
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""" Add 3x8 predecoder to the left of the origin and above any 2x4 decoders """
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# If we had 2x4 predecodes, those are used as the lower
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# decode output bits
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in_index_offset = num * 3 + self.no_of_pre2x4 * 2
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out_index_offset = num * 8 + self.no_of_pre2x4 * 4
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pins = []
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for input_index in range(3):
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pins.append("addr_{0}".format(input_index + in_index_offset))
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for output_index in range(8):
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pins.append("out_{0}".format(output_index + out_index_offset))
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pins.extend(["vdd", "gnd"])
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self.pre3x8_inst.append(self.add_inst(name="pre3x8_{0}".format(num),
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mod=self.pre3_8))
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self.connect_inst(pins)
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def place_pre_decoder(self):
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""" Creates pre-decoder and places labels input address [A] """
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for i in range(self.no_of_pre2x4):
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self.place_pre2x4(i)
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for i in range(self.no_of_pre3x8):
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self.place_pre3x8(i)
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def place_pre2x4(self,num):
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""" Place 2x4 predecoder to the left of the origin """
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if (self.num_inputs == 2):
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base = vector(-self.pre2_4.width,0)
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else:
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base= vector(-self.pre2_4.width, num * self.pre2_4.height)
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self.pre2x4_inst[num].place(base)
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def place_pre3x8(self,num):
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""" Place 3x8 predecoder to the left of the origin and above any 2x4 decoders """
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if (self.num_inputs == 3):
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offset = vector(-self.pre_3_8.width,0)
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mirror ="R0"
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else:
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height = self.no_of_pre2x4*self.pre2_4.height + num*self.pre3_8.height
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offset = vector(-self.pre3_8.width, height)
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self.pre3x8_inst[num].place(offset)
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def create_row_decoder(self):
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""" Create the row-decoder by placing NAND2/NAND3 and Inverters
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and add the primary decoder output pins. """
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if (self.num_inputs >= 4):
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self.create_decoder_nand_array()
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self.create_decoder_inv_array()
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def create_decoder_nand_array(self):
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""" Add a column of NAND gates for final decode """
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self.nand_inst = []
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# Row Decoder NAND GATE array for address inputs <5.
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if (self.num_inputs == 4 or self.num_inputs == 5):
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for i in range(len(self.predec_groups[0])):
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for j in range(len(self.predec_groups[1])):
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row = len(self.predec_groups[0])*j + i
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name = self.NAND_FORMAT.format(row)
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self.nand_inst.append(self.add_inst(name=name,
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mod=self.nand2))
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pins =["out_{0}".format(i),
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"out_{0}".format(j + len(self.predec_groups[0])),
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"Z_{0}".format(row),
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"vdd", "gnd"]
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self.connect_inst(pins)
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# Row Decoder NAND GATE array for address inputs >5.
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elif (self.num_inputs > 5):
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for i in range(len(self.predec_groups[0])):
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for j in range(len(self.predec_groups[1])):
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for k in range(len(self.predec_groups[2])):
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row = (len(self.predec_groups[0])*len(self.predec_groups[1])) * k \
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+ len(self.predec_groups[0])*j + i
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name = self.NAND_FORMAT.format(row)
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self.nand_inst.append(self.add_inst(name=name,
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mod=self.nand3))
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pins = ["out_{0}".format(i),
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"out_{0}".format(j + len(self.predec_groups[0])),
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"out_{0}".format(k + len(self.predec_groups[0]) + len(self.predec_groups[1])),
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"Z_{0}".format(row),
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"vdd", "gnd"]
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self.connect_inst(pins)
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def create_decoder_inv_array(self):
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"""
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Add a column of INV gates for the decoder.
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"""
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self.inv_inst = []
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for row in range(self.rows):
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name = self.INV_FORMAT.format(row)
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self.inv_inst.append(self.add_inst(name=name,
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mod=self.inv))
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self.connect_inst(args=["Z_{0}".format(row),
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"decode_{0}".format(row),
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"vdd", "gnd"])
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def place_decoder_inv_array(self):
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"""
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Place the column of INV gates for the decoder above the predecoders
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and to the right of the NAND decoders.
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"""
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z_pin = self.inv.get_pin("Z")
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if (self.num_inputs == 4 or self.num_inputs == 5):
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x_off = self.internal_routing_width + self.nand2.width
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else:
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x_off = self.internal_routing_width + self.nand3.width
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for row in range(self.rows):
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if (row % 2 == 0):
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inv_row_height = self.inv.height * row
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mirror = "R0"
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y_dir = 1
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else:
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inv_row_height = self.inv.height * (row + 1)
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mirror = "MX"
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y_dir = -1
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y_off = inv_row_height
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offset = vector(x_off,y_off)
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self.inv_inst[row].place(offset=offset,
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mirror=mirror)
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def place_row_decoder(self):
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"""
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Place the row-decoder by placing NAND2/NAND3 and Inverters
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and add the primary decoder output pins.
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"""
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if (self.num_inputs >= 4):
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self.place_decoder_nand_array()
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self.place_decoder_inv_array()
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self.route_decoder()
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def place_decoder_nand_array(self):
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""" Add a column of NAND gates for final decode """
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# Row Decoder NAND GATE array for address inputs <5.
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if (self.num_inputs == 4 or self.num_inputs == 5):
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self.place_nand_array(nand_mod=self.nand2)
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# Row Decoder NAND GATE array for address inputs >5.
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# FIXME: why this correct offset?)
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elif (self.num_inputs > 5):
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self.place_nand_array(nand_mod=self.nand3)
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def place_nand_array(self, nand_mod):
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""" Add a column of NAND gates for the decoder above the predecoders."""
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for row in range(self.rows):
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name = self.NAND_FORMAT.format(row)
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if ((row % 2) == 0):
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y_off = nand_mod.height*row
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y_dir = 1
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mirror = "R0"
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else:
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y_off = nand_mod.height*(row + 1)
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y_dir = -1
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mirror = "MX"
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self.nand_inst[row].place(offset=[self.internal_routing_width, y_off],
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mirror=mirror)
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def route_decoder(self):
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""" Route the nand to inverter in the decoder and add the pins. """
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for row in range(self.rows):
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# route nand output to output inv input
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zr_pos = self.nand_inst[row].get_pin("Z").rc()
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al_pos = self.inv_inst[row].get_pin("A").lc()
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# ensure the bend is in the middle
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mid1_pos = vector(0.5*(zr_pos.x+al_pos.x), zr_pos.y)
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mid2_pos = vector(0.5*(zr_pos.x+al_pos.x), al_pos.y)
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self.add_path("metal1", [zr_pos, mid1_pos, mid2_pos, al_pos])
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z_pin = self.inv_inst[row].get_pin("Z")
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self.add_layout_pin(text="decode_{0}".format(row),
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layer="metal1",
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offset=z_pin.ll(),
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width=z_pin.width(),
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height=z_pin.height())
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def route_predecode_rails(self):
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""" Creates vertical metal 2 rails to connect predecoder and decoder stages."""
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# This is not needed for inputs <4 since they have no pre/decode stages.
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if (self.num_inputs >= 4):
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input_offset = vector(0.5*self.m2_width,0)
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input_bus_names = ["predecode_{0}".format(i) for i in range(self.total_number_of_predecoder_outputs)]
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self.predecode_rails = self.create_vertical_pin_bus(layer="metal2",
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pitch=self.m2_pitch,
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offset=input_offset,
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names=input_bus_names,
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length=self.height)
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self.route_rails_to_predecodes()
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self.route_rails_to_decoder()
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def route_rails_to_predecodes(self):
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""" Iterates through all of the predecodes and connects to the rails including the offsets """
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# FIXME: convert to connect_bus
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for pre_num in range(self.no_of_pre2x4):
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for i in range(4):
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predecode_name = "predecode_{}".format(pre_num * 4 + i)
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out_name = "out_{}".format(i)
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pin = self.pre2x4_inst[pre_num].get_pin(out_name)
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self.route_predecode_rail_m3(predecode_name, pin)
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# FIXME: convert to connect_bus
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for pre_num in range(self.no_of_pre3x8):
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for i in range(8):
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predecode_name = "predecode_{}".format(pre_num * 8 + i + self.no_of_pre2x4 * 4)
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out_name = "out_{}".format(i)
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pin = self.pre3x8_inst[pre_num].get_pin(out_name)
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self.route_predecode_rail_m3(predecode_name, pin)
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def route_rails_to_decoder(self):
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""" Use the self.predec_groups to determine the connections to the decoder NAND gates.
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Inputs of NAND2/NAND3 gates come from different groups.
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For example for these groups [ [0,1,2,3] ,[4,5,6,7],
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[8,9,10,11,12,13,14,15] ] the first NAND3 inputs are connected to
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[0,4,8] and second NAND3 is connected to [0,4,9] ........... and the
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128th NAND3 is connected to [3,7,15]
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"""
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row_index = 0
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if (self.num_inputs == 4 or self.num_inputs == 5):
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for index_B in self.predec_groups[1]:
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for index_A in self.predec_groups[0]:
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# FIXME: convert to connect_bus?
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predecode_name = "predecode_{}".format(index_A)
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self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("A"))
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predecode_name = "predecode_{}".format(index_B)
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self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("B"))
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row_index = row_index + 1
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elif (self.num_inputs > 5):
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for index_C in self.predec_groups[2]:
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for index_B in self.predec_groups[1]:
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for index_A in self.predec_groups[0]:
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# FIXME: convert to connect_bus?
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predecode_name = "predecode_{}".format(index_A)
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self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("A"))
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predecode_name = "predecode_{}".format(index_B)
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self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("B"))
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predecode_name = "predecode_{}".format(index_C)
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self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("C"))
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row_index = row_index + 1
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def route_vdd_gnd(self):
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""" Add a pin for each row of vdd/gnd which are must-connects next level up. """
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# The vias will be placed in the center and right of the cells, respectively.
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xoffset = self.nand_inst[0].cx()
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for num in range(0,self.rows):
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for pin_name in ["vdd", "gnd"]:
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# The nand and inv are the same height rows...
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supply_pin = self.nand_inst[num].get_pin(pin_name)
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|
pin_pos = vector(xoffset, supply_pin.cy())
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self.add_power_pin(name=pin_name,
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|
loc=pin_pos)
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|
# Make a redundant rail too
|
|
for num in range(0,self.rows,2):
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|
for pin_name in ["vdd", "gnd"]:
|
|
start = self.nand_inst[num].get_pin(pin_name).lc()
|
|
end = self.inv_inst[num].get_pin(pin_name).rc()
|
|
mid = (start+end).scale(0.5,0.5)
|
|
self.add_rect_center(layer="metal1",
|
|
offset=mid,
|
|
width=end.x-start.x)
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|
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|
|
# Copy the pins from the predecoders
|
|
for pre in self.pre2x4_inst + self.pre3x8_inst:
|
|
self.copy_layout_pin(pre, "vdd")
|
|
self.copy_layout_pin(pre, "gnd")
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|
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|
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def route_predecode_rail(self, rail_name, pin):
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|
""" Connect the routing rail to the given metal1 pin """
|
|
rail_pos = vector(self.predecode_rails[rail_name].x,pin.lc().y)
|
|
self.add_path("metal1", [rail_pos, pin.lc()])
|
|
self.add_via_center(layers=("metal1", "via1", "metal2"),
|
|
offset=rail_pos,
|
|
rotate=90)
|
|
|
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|
|
def route_predecode_rail_m3(self, rail_name, pin):
|
|
""" Connect the routing rail to the given metal1 pin """
|
|
# This routes the pin up to the rail, basically, to avoid conflicts.
|
|
# It would be fixed with a channel router.
|
|
mid_point = vector(pin.cx(), pin.cy()+self.inv.height/2)
|
|
rail_pos = vector(self.predecode_rails[rail_name].x,mid_point.y)
|
|
self.add_via_center(layers=("metal1", "via1", "metal2"),
|
|
offset=pin.center(),
|
|
rotate=90)
|
|
self.add_wire(("metal3","via2","metal2"), [rail_pos, mid_point, pin.uc()])
|
|
self.add_via_center(layers=("metal2", "via2", "metal3"),
|
|
offset=rail_pos,
|
|
rotate=90)
|
|
|
|
|
|
def analytical_delay(self, slew, load = 0.0):
|
|
# A -> out
|
|
if self.determine_predecodes(self.num_inputs)[1]==0:
|
|
pre = self.pre2_4
|
|
nand = self.nand2
|
|
else:
|
|
pre = self.pre3_8
|
|
nand = self.nand3
|
|
a_t_out_delay = pre.analytical_delay(slew=slew,load = nand.input_load())
|
|
|
|
# out -> z
|
|
out_t_z_delay = nand.analytical_delay(slew= a_t_out_delay.slew,
|
|
load = self.inv.input_load())
|
|
result = a_t_out_delay + out_t_z_delay
|
|
|
|
# Z -> decode_out
|
|
z_t_decodeout_delay = self.inv.analytical_delay(slew = out_t_z_delay.slew , load = load)
|
|
result = result + z_t_decodeout_delay
|
|
return result
|
|
|
|
|
|
def input_load(self):
|
|
if self.determine_predecodes(self.num_inputs)[1]==0:
|
|
pre = self.pre2_4
|
|
else:
|
|
pre = self.pre3_8
|
|
return pre.input_load()
|