mirror of https://github.com/VLSIDA/OpenRAM.git
165 lines
6.3 KiB
Python
165 lines
6.3 KiB
Python
import design
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import debug
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from tech import drc, info
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from vector import vector
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import contact
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from ptx import ptx
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from globals import OPTS
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class single_level_column_mux(design.design):
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"""
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This module implements the columnmux bitline cell used in the design.
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Creates a single columnmux cell.
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"""
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def __init__(self, tx_size):
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name="single_level_column_mux_{}".format(tx_size)
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design.design.__init__(self, name)
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debug.info(2, "create single column mux cell: {0}".format(name))
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from importlib import reload
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c = reload(__import__(OPTS.bitcell))
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self.mod_bitcell = getattr(c, OPTS.bitcell)
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self.bitcell = self.mod_bitcell()
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self.ptx_width = tx_size * drc["minwidth_tx"]
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self.add_pin_list(["bl", "br", "bl_out", "br_out", "sel", "gnd"])
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self.create_layout()
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def create_layout(self):
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self.add_ptx()
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self.pin_height = 2*self.m2_width
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self.width = self.bitcell.width
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self.height = self.nmos2.uy() + self.pin_height
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self.connect_poly()
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self.add_bitline_pins()
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self.connect_bitlines()
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self.add_wells()
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def add_bitline_pins(self):
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""" Add the top and bottom pins to this cell """
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bl_pos = vector(self.bitcell.get_pin("bl").lx(), 0)
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br_pos = vector(self.bitcell.get_pin("br").lx(), 0)
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# bl and br
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self.add_layout_pin(text="bl",
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layer="metal2",
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offset=bl_pos + vector(0,self.height - self.pin_height),
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height=self.pin_height)
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self.add_layout_pin(text="br",
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layer="metal2",
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offset=br_pos + vector(0,self.height - self.pin_height),
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height=self.pin_height)
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# bl_out and br_out
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self.add_layout_pin(text="bl_out",
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layer="metal2",
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offset=bl_pos,
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height=self.pin_height)
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self.add_layout_pin(text="br_out",
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layer="metal2",
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offset=br_pos,
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height=self.pin_height)
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def add_ptx(self):
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""" Create the two pass gate NMOS transistors to switch the bitlines"""
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# Adds nmos1,nmos2 to the module
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self.nmos = ptx(width=self.ptx_width)
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self.add_mod(self.nmos)
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# Space it in the center
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nmos1_position = self.nmos.active_offset.scale(0,1) + vector(0.5*self.bitcell.width-0.5*self.nmos.active_width,0)
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self.nmos1=self.add_inst(name="mux_tx1",
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mod=self.nmos,
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offset=nmos1_position)
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self.connect_inst(["bl", "sel", "bl_out", "gnd"])
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# This aligns it directly above the other tx with gates abutting
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nmos2_position = nmos1_position + vector(0,self.nmos.active_height + self.poly_space)
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self.nmos2=self.add_inst(name="mux_tx2",
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mod=self.nmos,
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offset=nmos2_position)
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self.connect_inst(["br", "sel", "br_out", "gnd"])
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def connect_poly(self):
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""" Connect the poly gate of the two pass transistors """
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height=self.nmos2.get_pin("G").uy() - self.nmos1.get_pin("G").by()
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self.add_layout_pin(text="sel",
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layer="poly",
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offset=self.nmos1.get_pin("G").ll(),
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height=height)
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def connect_bitlines(self):
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""" Connect the bitlines to the mux transistors """
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# These are on metal2
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bl_pin = self.get_pin("bl")
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br_pin = self.get_pin("br")
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bl_out_pin = self.get_pin("bl_out")
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br_out_pin = self.get_pin("br_out")
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# These are on metal1
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nmos1_s_pin = self.nmos1.get_pin("S")
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nmos1_d_pin = self.nmos1.get_pin("D")
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nmos2_s_pin = self.nmos2.get_pin("S")
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nmos2_d_pin = self.nmos2.get_pin("D")
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# Add vias to bl, br_out, nmos2/S, nmos1/D
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=bl_pin.bc())
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=br_out_pin.uc())
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=nmos2_s_pin.center())
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=nmos1_d_pin.center())
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# bl -> nmos2/D on metal1
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# bl_out -> nmos2/S on metal2
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self.add_path("metal1",[bl_pin.ll(), vector(nmos2_d_pin.cx(),bl_pin.by()), nmos2_d_pin.center()])
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# halfway up, move over
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mid1 = bl_out_pin.uc().scale(1,0.5)+nmos2_s_pin.bc().scale(0,0.5)
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mid2 = bl_out_pin.uc().scale(0,0.5)+nmos2_s_pin.bc().scale(1,0.5)
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self.add_path("metal2",[bl_out_pin.uc(), mid1, mid2, nmos2_s_pin.bc()])
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# br -> nmos1/D on metal2
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# br_out -> nmos1/S on metal1
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self.add_path("metal1",[br_out_pin.uc(), vector(nmos1_s_pin.cx(),br_out_pin.uy()), nmos1_s_pin.center()])
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# halfway up, move over
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mid1 = br_pin.bc().scale(1,0.5)+nmos1_d_pin.uc().scale(0,0.5)
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mid2 = br_pin.bc().scale(0,0.5)+nmos1_d_pin.uc().scale(1,0.5)
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self.add_path("metal2",[br_pin.bc(), mid1, mid2, nmos1_d_pin.uc()])
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def add_wells(self):
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"""
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Add a well and implant over the whole cell. Also, add the
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pwell contact (if it exists)
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"""
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# Add it to the right, aligned in between the two tx
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active_pos = self.nmos2.lr().scale(0,0.5) + self.nmos1.ur().scale(1,0.5)
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self.add_via_center(layers=("active", "contact", "metal1"),
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offset=active_pos,
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implant_type="p",
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well_type="p")
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# Add the M1->M2->M3 stack
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=active_pos)
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self.add_via_center(layers=("metal2", "via2", "metal3"),
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offset=active_pos)
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self.add_layout_pin_rect_center(text="gnd",
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layer="metal3",
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offset=active_pos)
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